Packaging substrate manufacturing process, packaging substrate and chip packaging structure
A packaging substrate and manufacturing process technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., can solve product yield and product cost difficult control, high precision requirements, complex manufacturing process, etc. problems, to achieve the effect of improving product accuracy and yield, shortening the process, and reducing costs
Active Publication Date: 2022-03-04
SHENZHEN ZHIJIN ELECTRONICS
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Problems solved by technology
[0003] In order to overcome the deficiencies of the prior art, one of the purposes of the present invention discloses a packaging substrate manufacturing process, which is used to solve the existing complex manufacturing process of the packaging substrate, high precision requirements in the assembly process, and high product yield and product cost. Difficult to manage
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[0046] Below, the present invention will be further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of not conflicting, the various embodiments described below or the technical features can be combined arbitrarily to form new embodiments. .
[0047] see Figure 1-2 , a packaging substrate manufacturing process S100 disclosed in an embodiment of the present invention is used to manufacture a packaging substrate for chip packaging, and the packaging substrate manufacturing process S100 includes:
[0048] Step S10, laminating and pressing the first conductive sheet 10 with the conductive protrusion 11 on one side and the insulating member 20 with the receiving cavity 21 on one side in such a way that the conductive protrusion 11 is opposite to the receiving cavity 21, and making the conductive protrusion 11 Stored in the housing cavity 21, the second conductive sheet 30 is stacked and pressed...
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The invention discloses a manufacturing process of a packaging substrate, a packaging substrate and a chip packaging structure, wherein the manufacturing process of the packaging substrate is performed by laminating and pressing a first conductive sheet, an insulating member and a second conductive sheet, and conductive bumps are arranged on the first conductive sheet , the insulator is provided with accommodating cavities for accommodating conductive bumps, by making lead wires connecting the conductive bumps and the second conductive sheet, by processing the second conductive sheet into wiring bumps for external line connection, and by A mounting groove for chip mounting and a conductive bump for chip wiring are formed in the receiving cavity. In this way, compared with the existing way of mounting the chip on the packaging substrate and then adding a receiving cavity bracket, the packaging substrate The manufacturing process can form a packaging substrate with a packaging circuit and a chip packaging cavity at one time, which can not only effectively shorten the process and reduce costs, but also effectively reduce the difficulty of processing, thereby improving product accuracy and yield.
Description
technical field [0001] The invention relates to the field of chip packaging, in particular to a manufacturing process of a packaging substrate, a packaging substrate and a chip packaging structure using the packaging substrate. Background technique [0002] As the development of sensor technology matures, its application scenarios become more and more complex. In order to achieve more stable and excellent signal transmission performance, it is usually necessary to package the chip in a housing cavity. At present, the traditional implementation method is to mount the chip on the packaging substrate and then add a housing cavity bracket. This implementation method not only has a complicated process, but also requires high precision during the assembly process, and it is difficult to control the product yield and product cost. Contents of the invention [0003] In order to overcome the deficiencies of the prior art, one of the purposes of the present invention discloses a pac...
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IPC IPC(8): H01L21/48H01L23/492H01L23/498
CPCH01L2224/48091H01L2224/48227H01L2924/00014
Inventor 康孝恒蔡克林倪超李瑞邱龙洲许凯
Owner SHENZHEN ZHIJIN ELECTRONICS