High-voltage electrostatic discharge clamping protection element and integrated circuit chip
A clamp protection, high-voltage electrostatic technology, applied in the direction of electrical components, circuits, electric solid devices, etc., can solve the problem of low anti-static discharge ability, improve endurance and reliability, avoid leakage phenomenon and fast reverse The effect of the phenomenon
Active Publication Date: 2019-07-05
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
Therefore, the anti-static discharge capability of the electrostatic discharge clamp protection element is relatively low, and it is urgent to provide a high-voltage electrostatic discharge clamp protection element with high performance and high tolerance in practice.
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[0027] The technical content of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0028] The existing high-voltage electrostatic discharge clamping protection element is a stack structure composed of a plurality of PMOS transistors. The stack structure composed of three PMOS transistors is taken as an example to expand the description below. like figure 1 As shown, each PMOS transistor is composed of a first N+ doped region 2, a first P+ doped region 3, a second P+ doped region 4 and an N-type well 5; wherein, the first N+ doped region 2, the first The P+ doping region 3 and the second P+ doping region 4 are arranged on the N-type well 5, the first N+ doping region 2 forms the substrate terminal of the PMOS transistor, and the first P+ doping region 3 forms the source terminal of the PMOS transistor, The second P+ doping region 4 forms the drain terminal of the PMOS transistor, and a gate...
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The invention discloses a high-voltage electrostatic discharge clamping protection element. The high-voltage electrostatic discharge clamping protection element comprises a plurality of low-voltage NMOS transistors and current trigger structures corresponding to the low-voltage NMOS transistors, wherein each low-voltage NMOS transistor is connected with the corresponding current trigger structure.The input end of the high-voltage electrostatic discharge clamping protection element is connected with an electrostatic discharge signal, and the output end of the high-voltage electrostatic discharge clamping protection element is grounded. The current trigger structure is used for starting the high-voltage electrostatic discharge clamping protection element before the electrostatic discharge signal reaches the high-voltage electrostatic discharge clamping protection element. By the adoption of the integrated circuit chip, the electric leakage phenomenon and the fast reverse phenomenon areeffectively avoided, and the tolerance and reliability of anti-static discharge of the integrated circuit chip are improved.
Description
technical field [0001] The invention relates to a high-voltage electrostatic discharge clamping protection element and an integrated circuit chip including the high-voltage electrostatic discharge clamping protection element, which belongs to the technical field of integrated circuits. Background technique [0002] Currently, more and more integrated circuit chips are implemented using complementary metal-oxide-semiconductor (CMOS) technology to achieve the lowest possible power consumption. Since transistors on an integrated circuit chip operate in different voltage domains, they must have different doping concentrations and different gate thicknesses. Therefore, in order to ensure that the integrated circuit chip is not damaged by the current peak or voltage peak, it is necessary to protect the integrated circuit chip from electrostatic discharge. [0003] At present, in the field of integrated circuits, electrostatic discharge clamping protection components are generally...
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IPC IPC(8): H01L27/02H01L29/06
CPCH01L27/0266H01L29/0603H01L29/0684
Inventor 谷欣明陈捷朱恺
Owner SEMICON MFG INT (SHANGHAI) CORP