Memory and preparation method thereof

Abstract

The invention discloses a memory and a preparation method thereof. The memory comprises a substrate, an isolation layer, a groove structure, floating gates, a dielectric layer, and a control gate, wherein the substrate comprises a plurality of active regions and a plurality of shallow trench isolation regions, and the active regions and the shallow trench isolation regions are arranged at intervals; the isolation layer is filled in the shallow trench isolation regions, wherein the isolation layer extends to a part of the upper surfaces, close to one side of the shallow trench isolation regions, of the active regions; the groove structure is located in the active regions, and the groove structure partially penetrates through the substrate corresponding to the active regions; the floating gates are located on the surface of the inner wall of the groove structure and extend to the upper surface of the isolation layer along the inner wall of the groove structure, and the floating gates corresponding to the adjacent active regions are disconnected; the dielectric layer is located on the upper surfaces of the floating gates and the upper surface of the isolation layer; and the control gate located on the dielectric layer. The memory provided by the embodiment of the invention has relatively low power consumption and relatively high yield and reliability.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor manufacturing, and in particular, to a memory and a manufacturing method thereof. Background technique [0002] Traditional Flash memories use self-alignment technology to make floating gates (Floating Gate, FG). Although the process is simple and the cost is low, the effective contact area between the floating gate and the control gate (Control Grid, CG) is low, resulting in CG-FG coupling The capacitance is low, which leads to the control gate requiring a higher operating voltage to erase and write the floating gate, resulting in high power consumption of the storage device. In addition, the stacking thickness of the traditional floating gate and control gate is thicker in the vertical direction. As a result, it is difficult to fill the subsequent intermediate insulating dielectric layer, resulting in problems of low yield and poor reliability. Contents of the inven...

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Problems solved by technology

[0002] Traditional Flash memories use self-alignment technology to make floating gates (Floating Gate, FG). Although the process is simple and the cost is low, the effective contact area between the floating gate and the control gate (Control Grid, CG) is low, resulting in CG-FG coupling The capacitance is low, which leads to the control gate requiring a higher operating voltage to erase and write the floating gate, resulting in high power consumption of the storage device. In addition, the stacking thickness of the traditional floating gate and control gate is thicker in the vertical direction. It leads to difficulty in filling the subsequent intermediate insulating dielectric layer, resulting in problems of low yield and poor reliability

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