Delay correction method, circuit and device, equipment and computer readable storage medium

Abstract

The invention discloses a delay correction method, a delay correction circuit, a delay correction device, delay correction equipment and a computer readable storage medium. The method comprises the steps that a first sampling clock delay value is set, data sampling is carried out to obtain first sampling data, and the first sampling clock delay value is used for controlling delay of a first sampling clock to determine a first sampling point of a first data sampling window; setting a second sampling clock delay value and performing data sampling to obtain second sampling data, the second sampling clock delay value being used for controlling the delay of a second sampling clock to determine a second sampling point of a second data sampling window; and changing the second sampling clock delayvalue, and correcting the first sampling clock delay value according to a comparison result of the first sampling data and the second sampling data. According to the technical scheme, the effective data sampling window can be adaptively tracked, and the memory controller can stably read the data from the memory particles in various environments on the premise that the production difficulty is notincreased, the cost is not increased and the memory bandwidth is not influenced.

Description

technical field [0001] The present disclosure relates to the technical field of signal processing, and in particular to a delay correction method, circuit, device, equipment and computer-readable storage medium. Background technique [0002] Under modern computer architecture, two main factors affecting system performance are the computing power of the central processing unit (CPU) and the access efficiency of memory. After years of development, the computing power of the CPU has made considerable progress, but the improvement of memory technology has not kept pace with the development of the CPU, which has become the main bottleneck of the current computer performance improvement. Nowadays, the processing power of the CPU has far exceeded the data throughput rate of the memory. When the data has not been read back from the memory, the CPU can only be in an idle state. In order to solve this bandwidth mismatch problem, CPU generally adopts a multi-level cache strategy to tr...

AI Technical Summary

Problems solved by technology

In order to solve this bandwidth mismatch problem, CPU generally adopts a multi-level cache strategy to transfer the data that the CPU may need from the memory to the on-chip cache in advance, so that when the CPU needs to use these data, it can be efficiently directly from the cache. Read, but the cost of on-chip cache with the same data capacity is much higher than that of off-chip memory particles, so the cost of adopting a multi-level cache strategy is the increase in cost, and it cannot fundamentally solve the impact of memory access efficiency on system performance

[0003] In order to improve memory access efficiency, there are mainly two solutions in the prior art. One is to increase the data bit width of the memory, such as HBM technology. The advantage of this solution is that it can obtain a larger bandwidth with a lower clock frequency and The power consumption is also low, but because it needs to use stacking technology, it is difficult to produce and the cost is high. At present, it is basically only used in high-end graphics cards; the other is to increase the data rate of memory, such as GDDR6 (Graphics Double Data Rate, version 6 , the 6th generation double data transfer rate memory) technology, the advantage of this solution is that the production process is mature and the cost is low, but the effective sampling window of the data will be very small due to the increase of the clock frequency, such as 16Gbps GDDR6, its effective data The theoretical value of the sampling window is only 62.5ps. In addition, high-speed signals will be affected in various ways during actual use. The truly effective sampling window may not reach 30ps. This poses a great challenge to the design of the memory controller. challenge

[0004] In addition, in order to enable the memory controller to correctly read data from GDDR particles, the GDDR technical specification provides a data training method to help the memory controller find an effective data sampling window, but this method requires memory bandwidth , so it is generally only done once during the initialization of GDDR particles, and will not be done again during the normal operation of GDDR particles

At the same time, since the temperature, voltage and other conditions of the GDDR particles will change during the working process, this will also cause the effective data sampling window of the GDDR particles to shift. Once the data cannot be read correctly from the GDDR particles, the memory controller must not Do not stop the normal work, and re-find the effective data sampling window, which will cause the loss of memory bandwidth

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