Wafer bonding structure and method for manufacturing same
A wafer bonding and wafer technology, which is used in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc. The effect of reducing the surface area
Inactive Publication Date: 2019-08-09
HUAIAN IMAGING DEVICE MFGR CORP
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- Application Information
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When the recess 20 formed by the bonding process is larger than the design specification, it will affect the electrical performance of the bonded device
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[0032] The following description provides specific application scenarios and requirements of the application, with the purpose of enabling those skilled in the art to manufacture and use the contents of the application. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and embodiments without departing from the spirit and scope of the disclosure. application. Thus, the present disclosure is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
[0033] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the accompanying drawings.
[0034] An embodiment of the present application provides a method for forming a wafer bonding structure, including: providing a first wafer, forming a first dielectric layer on the first wafer...
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The application provides a wafer bonding structure and a method for forming the same. The wafer bonding structure includes a first wafer; a first dielectric layer on the first wafer; a metal interconnection structure in the first dielectric layer and divided into at least two partially connected sub-metal interconnect structures. According to the wafer bonding structure and the forming method thereof, the surface of the metal interconnect structure is divided into at least two partially connected sub-metal interconnect structures, which not only realize the electrical connection between the two sub0metal interconnect structures, but also reduces the surface area of a bonding surface, and improves the quality of the electrical connection between the wafers.
Description
technical field [0001] The present application relates to the field of semiconductor manufacturing, in particular, to a wafer bonding structure and a method for manufacturing the wafer bonding structure. Background technique [0002] Wafer level Cu-Cu bonding (Wafer level Cu-Cu bonding) is an interconnection technology between wafers. This interconnection technology aligns and bonds at least one pair of copper interconnection structures to achieve multiple Electrical connection of copper interconnect structures between wafers. [0003] The copper interconnection structure refers to the attached figure 1 As shown, it includes a first wafer 100, a first dielectric layer 101 located on the first wafer 100 and a first copper interconnection structure 102 located in the first dielectric layer 101, because the first copper interconnection In the forming process of the structure 102 , CMP is used to grind the copper interconnection structure, and the surface of the first copper i...
Claims
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IPC IPC(8): H01L21/768H01L23/538
CPCH01L24/20H01L24/19H01L24/80H01L2224/8034H01L2224/05554H01L2224/05552H01L2224/02125H01L2224/0215H01L2224/80895H01L2224/80896H01L2224/05576H01L2224/05647H01L2224/05686H01L24/05H01L24/08H01L2224/03452H01L2224/0348H01L2224/05546H01L2224/05624H01L2224/05684H01L24/03H01L21/76816H01L23/5283H01L2224/08145H01L2924/00012H01L2924/05442H01L2924/00014
Inventor 沈新林王海宽洪波郭松辉林宗贤
Owner HUAIAN IMAGING DEVICE MFGR CORP