Package substrate and method of forming the same

Abstract

A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased.

Description

technical field [0001] The present disclosure relates to a package substrate, in particular to a package substrate embedded with an interposer and a manufacturing method thereof. Background technique [0002] As electronic products become thinner, thinner and smaller, and their functions are continuously improved, the wiring density of the chip is getting higher and higher, and the unit of nanometer size, so the distance between the contacts on the chip is extremely small. However, at present, the pitch of the electrical contacts of the flip-chip package substrate is in the unit of micrometers, so it cannot be effectively reduced to the size corresponding to the pitch of the chip contacts. As a result, although there are semiconductor chips with high circuit density, there are no compatible chips. Encapsulate the substrate so that it cannot effectively produce electronic products. [0003] In order to overcome the above problems, a silicon interposer (Silicon interposer) is...

AI Technical Summary

Problems solved by technology

[0007] However, because the diameter of the conductive TSVs 100 is too large, it is difficult to increase the layout density of the conductive TSVs 100 in the silicon interposer 10.

[0008] In addition, if the end surface diameter r' of the conductive TSV 100' is to be less than 80 μm (eg, 50 μm) in order to increase the layout density and reduce the cost, i

Images