Debugging information output method and device in software and hardware collaborative verification

Abstract

The invention provides a debugging information output method and device in software and hardware collaborative verification, and the method comprises the steps: enabling a virtual display terminal tobe hung on a parallel bus in a SoC verification simulation environment, and enabling standard output equipment of debugging information to be redirected to the virtual display terminal; and outputtingthe debugging information to the virtual display terminal in response to a printing output instruction of the debugging information, and directly printing and outputting the debugging information onthe virtual display terminal by adopting a preset hardware description language. By utilizing the method and the device, the output efficiency and speed of debugging information in software and hardware collaborative verification can be remarkably improved.

Description

technical field [0001] The invention belongs to the verification field, and in particular relates to a method and a device for outputting debugging information in software and hardware collaborative verification. Background technique [0002] With the emergence of design technology centered on IP (Intellectual Property, Intellectual Property) core multiplexing, integrated circuit application design has entered the era of System on a Chip (SoC for short). SoC is a highly concentrated embedded system-on-chip. Any defect in the chip design summary will lead to the design failure of the entire chip. Therefore, before tape-out, the system function of the chip must be verified. Among them, software-hardware co-verification is the core technology of SoC design. The so-called software-hardware co-verification refers to Before a physical prototype of the hardware (circuit board or chip) is produced, the software is run through a system model to check for errors in the hardware desig...

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Problems solved by technology

[0003] In the traditional software debugging process in embedded systems, the output information of the printing function is usually used to display the terminal using the Universal Asynchronous Receiver / Transmitter (UART for short) interface, that is, the output characters are transmitted to the display terminal through the UART interface. On the output display terminal, the efficiency of the output process is relatively slow. The reasons include: (1) UART is a kind of asynchronous serial port communication protocol. The working principle is to transmit each character of the transmitted data one by one. The unit of the American Standard Code for Information Interchange (ASCII), each character output process needs to be converted into an 8-bit serial signal, and the UART transmission process also needs to increase the start bit, parity bit and stop bits

(2) The UART serial communication interface is used as a low-speed peripheral interface, and its transmission speed itself is relatively low

(3) The basis of software-hardware co-verification runs on an RTL-level hardware simulation platform, and its execution process is based on event response. For example, a clock trigger process requires the entire design platform to trigger an event once, so when the design scale is large In this case, the hardware simulation load that needs to be actually executed for each printout process will become very large, and if it is a gate-level simulation, the simulation time will become very long

[0004] It can be seen from this that there is a problem of low debugging information output efficiency in SoC hardware and software co-verification in the prior art

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