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Superjunction MOS device structure and its fabrication method

A MOS device, conductive type technology, applied in the field of superjunction MOS device structure and its preparation, can solve problems such as device failure, device oscillation, electromagnetic interference, etc., and achieve the effect of improving stability and reducing device power consumption

Active Publication Date: 2022-06-24
上海功成半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a super junction MOS device structure and its preparation method, which is used to solve the problem that the existing super junction MOS device structure is easily caused by a sharp change in capacitance during the switching process. Oscillation and electromagnetic interference in the device may even cause problems such as device failure

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  • Superjunction MOS device structure and its fabrication method
  • Superjunction MOS device structure and its fabrication method
  • Superjunction MOS device structure and its fabrication method

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Embodiment 1

[0055] like figure 2As shown, this embodiment provides a superjunction MOS device structure, which includes: a first conductivity type substrate 11; a first conductivity type epitaxial layer 12 located on the surface of the first conductivity type substrate 11; a plurality of first conductivity type substrates 11; Two conductive type pillars 13 are distributed in the first conductive type epitaxial layer 12 at intervals, so that first conductive type pillars 14 are spaced between each of the second conductive type pillars 13 and separated from the first conductive type pillars 14 and the second conductivity type pillars 13 are alternately arranged to form a superjunction structure, the second conductivity type is different from the first conductivity type; a plurality of second conductivity type well regions 15 are located in the first conductivity type epitaxial layer 12, and located on the upper surface of the second conductive type pillar 13 , and the second conductive typ...

Embodiment 2

[0070] like image 3 As shown, the present invention also provides a method for fabricating a superjunction MOS device structure, which can be used to fabricate the superjunction MOS device structure in the first embodiment, so the description of the same structure in the embodiment is also applicable to this embodiment. The preparation method at least comprises the following steps:

[0071] Step S1: providing a first conductive type substrate 11, and forming a first conductive type epitaxial layer 12 on the surface of the first conductive type substrate 11;

[0072] Step S2 : forming a plurality of trenches distributed at intervals in the first conductive type epitaxial layer 12 , and a plurality of the trenches are separated by a plurality of first conductive type pillars 14 in the first conductive type epitaxial layer 12 ;

[0073] Step S3: Fill the trenches to form a plurality of second conductivity type pillars 13, the second conductivity type pillars 13 and the first c...

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Abstract

The invention provides a super junction MOS device structure and a preparation method thereof. The device structure includes: a substrate of the first conductivity type; an epitaxial layer of the first conductivity type; a plurality of pillars of the second conductivity type distributed in the epitaxial layer of the first conductivity type at intervals so as to space out a second conductivity type pillar between the pillars of the second conductivity type A super junction structure is formed by a conductive type column; a plurality of second conductive type well regions; a first conductive type source region; a second conductive type well lead-out region; a gate oxide layer; a negative capacitance material layer; a gate conductive layer; an interlayer The dielectric layer; the source metal layer is located on the surface of the second conductivity type well lead-out region and the surface of the first conductivity type source region; the drain metal layer is located on the surface of the first conductivity type substrate away from the first conductivity type epitaxial layer. The present invention can effectively prevent sudden changes in the reverse output capacitance (Coss) and reverse transmission capacitance (Crss) of the superjunction MOS device structure during the switching process, prevent device oscillation, improve its EMI characteristics, and improve device stability.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a superjunction MOS device structure and a preparation method thereof. Background technique [0002] Since the super-junction transistor (Super-Junction MOS, SJ-MOS for short) structure was first proposed in the late 1980s, the super-junction MOS device has attracted the attention of the industry due to its advantages of small on-resistance, fast turn-on speed and low switching loss. has received extensive attention, and its structure has been continuously optimized. In the existing superjunction transistor, a doped region composed of a series of P-type and N-type semiconductor thin layers alternately arranged to replace the single light doping in the traditional VDMOS (Vertical double-diffused MOSFET, vertical double-diffused metal oxide semiconductor) device complex drift region. In the off state, due to the mutual compensation effect of the electric fields i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/51H01L21/336
CPCH01L29/7802H01L29/516H01L29/66712
Inventor 罗杰馨薛忠营柴展徐大朋肖兵
Owner 上海功成半导体科技有限公司