Etching method of semiconductor device and three-dimensional memory

Abstract

The invention discloses an etching method of a semiconductor device and a three-dimensional memory. The etching method comprises the steps of providing a to-be-etched semiconductor structure, whereinthe semiconductor structure comprises at least one semiconductor substrate, a laminated structure located on the semiconductor substrate and first conductive columns located in the laminated structure; and the first conductive columns are conductively connected with the semiconductor substrate; forming an insulating layer coating the semiconductor substrate to avoid an exposed area on the surfaceof the semiconductor substrate; and etching the laminated structure by adopting a dry etching process and forming slits penetrating into the laminated structure, thereby ensuring that the dry etchingprocess is carried out in the expected direction and improving the yield and the working stability of the device.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to an etching method for semiconductor devices and a three-dimensional memory. Background technique [0002] Memory is a memory device used to save information in modern information technology. With the continuous improvement of the demand for integration and data storage density of various electronic devices, it is becoming more and more difficult for ordinary two-dimensional memory devices to meet the requirements. In this case, three-dimensional (3D) memory comes into being. [0003] At present, in the preparation process of a three-dimensional memory, generally a semiconductor substrate is provided first and a stacked structure is formed on the semiconductor substrate; then, the stacked structure is etched by a dry etching process to form a layer exposing the semiconductor substrate. Channel hole (Chanel Hole, CH), and a channel structure is formed in...

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Problems solved by technology

[0004] However, the researchers found that in the process of forming GLS by dry etching process, the etching often cannot be performed along the direction vertical to the semiconductor substrate as expected, but tends to be inclined towards the CH direction; especially in the 90-layer In the above 3D NAND memory structure, the tilt phenomenon of GLS is more serious

This reduces the yield rate of the device to a certain extent and affects the stability of the device operation; in addition, due to the inclination of the GLS, the distance between the CH and the GLS cannot be further reduced, which brings obstacles to the layout of the three-dimensional memory array area.

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