Planarization processing method, preparation method of three-dimensional memory and three-dimensional memory

Abstract

The embodiment of the invention discloses a planarization processing method, a preparation method of a three-dimensional memory and the three-dimensional memory. The planarization processing method comprises the steps: providing a semiconductor structure to be processed, wherein the semiconductor structure at least comprises a laminated structure and a plug, and the plug is provided with a first part inserted into the laminated structure and a second part protruding out of the upper surface of the laminated structure; removing the second part to expose a first sacrificial layer on the upper surface of the laminated structure; completely removing the first sacrificial layer by adopting a first etching process to expose a first dielectric layer below the first sacrificial layer in the laminated structure; and depositing a second dielectric layer on the first dielectric layer, and carrying out planarization processing on the surface of the second dielectric layer. Therefore, the process cost can be reduced, the residue of the first sacrificial layer is avoided, and the performance of the three-dimensional memory is improved.

Description

technical field [0001] The embodiments of the present application relate to the field of semiconductor devices and their manufacture, and relate to, but are not limited to, a planarization processing method, a method for preparing a three-dimensional memory, and a three-dimensional memory. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, the industry has developed a memory with a three-dimensional structure, and the integration density is increased by three-dimensionally arranging memory cells on a substrate. [0003] At present, for the planarization treatment of three-dimensional memory, the part of the plug protruding from the upper surface of the stacked structure in the semiconductor structure forming the three-dimensional memory is usually removed by chemical mechanical polishing (CMP) process, and after removing the plug After the part of the plug is removed, the sacrificial layer exposed by the stacked structure is...

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Problems solved by technology

[0004] But, when adopting the CMP process to remove the sacrificial layer exposed by the laminated structure, the cost of the whole process will be increased due to the high price of the sacrificial layer CMP abrasive; Uniformity will make the surface of the sacrificial layer on the uppermost layer of the stacked structure uneven and form a stepped structure, and the material of the sacrificial layer cannot be completely ground away by the CMP process at the stepped structure, which will easily cause the sacrificial layer to remain, which will have a great impact Performance of 3D memory

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