Nonvolatile memory and manufacturing method thereof

Abstract

The invention relates to a nonvolatile memory and a manufacturing method thereof. The non-volatile memory includes a memory cell array and an intermediate string selection tube without memory cells. The memory cell array comprises a plurality of memory strings, each memory string comprises a first sub-string and a second sub-string which are connected in series, and the first sub-string and the second sub-string respectively comprise a plurality of memory cells. And the intermediate string selection tube is connected between the first sub-string and the second sub-string. According to the nonvolatile memory, the intermediate string selection tube without the memory cell is connected between the memory strings, and during programming, the channel potential of the non-selected memory cell can be improved by applying a relatively high voltage to the intermediate string selection tube, so that the interference of programming operation on the non-selected memory cell is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a nonvolatile memory and a manufacturing method thereof. Background technique [0002] With the development of technology, the size requirements of electronic products are getting smaller and smaller, and at the same time, requirements for small volume and high capacity are put forward for storage devices. Non-volatile memory can retain stored data when power is interrupted. In order to improve the integration level of nonvolatile memory, a 3D nonvolatile memory device in which memory cells are stacked vertically from a silicon substrate is proposed. [0003] For the 3D NAND non-volatile memory with a vertical channel structure, it has a stack structure formed by alternately stacking dielectric layers and gate layers and a channel hole running through the stack structure. As the number of stacked layers increases, deep hole etching becomes more and more difficult....

AI Technical Summary

Problems solved by technology

Due to the deep channel holes formed by connecting multiple stack structures, the thickness of the functional layer formed after one pad will be inconsistent up and down, and the consistency of the components of each layer will be relatively poor, resulting in poor electrical performance of the memory

On the other hand, due to the increase in the number of layers, the problem of program disturbance in the programming phase of the non-volatile memory with multiple stack structures will be more serious

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