Methods of forming a semiconductor structure and methods of forming isolation structures

Abstract

The present invention relates to a method of reducing silicon consumption of a silicon material. The method comprises the steps of: cleaning a silicon material and subjecting the cleaned silicon material to a vacuum anneal at a temperature below a melting point of silicon and under vacuum conditions. The silicon material is subjected to additional process acts without substantially removing silicon of the silicon material. Additional methods of forming a semiconductor structure and forming isolation structures are also disclosed.

Description

[0001] priority claim [0002] This application claims a 2018 application for "Methods for Reducing Silicon Consumption, Methods of Forming a Semiconductor Structure, and Methods of Forming Isolation Structures" The benefit of the filing date of U.S. Patent Application Serial No. 15 / 982,872, filed May 17. technical field [0003] Embodiments disclosed herein relate to semiconductor fabrication, including the fabrication of semiconductor devices, such as dynamic random access memory (DRAM) device fabrication. More particularly, embodiments of the present invention relate to methods of minimizing silicon loss during semiconductor device fabrication, methods of forming semiconductor structures, and methods of forming isolation structures. Background technique [0004] An integrated circuit contains a number of electronic devices, such as transistors or capacitors, in an active area of ​​a substrate. In most cases, the active area comprises silicon, and the various integrated...

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Therefore, the main effect of the process is to consume silicon, reducing the active area efficiency

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