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Clock Tree Synthesis Method

A technology of clock tree synthesis and clock unit, which is applied in the direction of generating/distributing signals, can solve problems such as small intervals and circuits that cannot pass the test, and achieve the effects of easy testing, improved life and stability

Active Publication Date: 2021-08-17
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, even if proper spacing between clock cells has been reserved during floorplanning, parameters corresponding to these spacings, such as clock cell spacing, are not available to physical implementation tools. Mandatory, in other words, these parameters are soft constraints rather than hard constraints, so these intervals may become too small after clock tree synthesis, causing the circuit to fail the test

Method used

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Embodiment Construction

[0016] The technical terms in the following explanations refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations of these terms shall be based on the descriptions or definitions in this specification.

[0017] Part or all of the process of the clock tree synthesis method of the present invention may be in the form of software and / or firmware. Under the premise of not affecting the full disclosure and practicability of the method invention, the description of the following method invention will focus on the steps. rather than hardware.

[0018] figure 2 It is a flowchart of an embodiment of the clock tree synthesis method of the present invention. The step of layout planning (step S210 ) includes selecting clock cells from a clock cell library. This step determines the driving force of the clock cell, in other words, this step selects the clock cell according to the required driving force. However,...

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Abstract

The invention discloses a clock tree synthesis method, comprising: determining a driving force of a clock unit; determining a reserved space corresponding to the clock unit according to the driving force; generating the clock unit and the reserved space, wherein the reserved space and the reserved space are The clock unit is adjacent; a decoupling capacitor filling unit is set in the reserved space, wherein the area and / or capacitance value of the decoupling capacitor filling unit is related to the driving force; and the property of the clock unit and the decoupling are fixed. Properties of the capacitor fill unit.

Description

technical field [0001] The present invention relates to clock trees, and more particularly to clock tree synthesis methods. Background technique [0002] Clock trees are commonly found in today's integrated circuits, figure 1 It is a schematic diagram of a conventional circuit layout, which includes two clock trees—a clock tree 112 and a clock tree 122 . The clock tree 112 is composed of a plurality of clock cells 115 , and the clock tree 122 is composed of a plurality of clock cells 125 . A clock unit is, for example, an inverter or a buffer. The clock tree 112 is electrically connected to the PLL 110 , and the PLL 110 provides clocks to the register 132 and the register 134 through the clock tree 112 . The clock tree 122 is electrically connected to the PLL 120 , and the PLL 120 provides clocks to the register 136 and the register 138 through the clock tree 122 . The logic circuit 140 is coupled between the register 132 and the register 134 and forms a data path thereb...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/04
CPCG06F1/04
Inventor 刘恩诚蔡宜青张云智
Owner REALTEK SEMICON CORP