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Clock control circuit and method

A clock control and circuit technology, applied in the electronic field, can solve problems such as timing convergence

Active Publication Date: 2021-09-14
SHENZHEN INTELLIFUSION TECHNOLOGIES CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The invention provides a timing control circuit, aiming to solve the problem of timing convergence of the existing timing control circuit

Method used

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  • Clock control circuit and method
  • Clock control circuit and method

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Embodiment Construction

[0022] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0023] figure 1 The circuit diagram of the clock control circuit provided by the first embodiment of the present invention is shown. For the convenience of description, only the parts related to the embodiment of the present invention are shown, and the details are as follows:

[0024] Such as figure 1 As shown, the clock control circuit 100 includes a clock source 10, a first buffer unit 20, a first register group 30, a combinational logic unit 40, a second buffer unit 50, a plurality of gated clock units 60, a second register group 70 and a third buffer unit 80 . For ease of understanding, in ...

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Abstract

The present invention discloses a clock control circuit and method. The clock control circuit includes: a clock source, a first buffer unit, a first register group, a combinational logic unit, a second buffer unit, K gated clock units, a first Three buffer units and T second register groups; the third buffer unit includes a plurality of third buffers for forming K M-level N branch structures; the clock source passes through the first buffer in sequence The unit, the first register group, and the combinational logic unit are connected to the K gated clock units, and are also connected to the K gated clock units through the second buffer unit; each gated clock unit through an M-level N-branch structure formed of N M‑1 branches and N M‑1 The second register group is connected; among them, K, M, N, T are all positive integers, and T≤K×N M‑1 ≤T+N M‑1 ‑1, when T is constant, the larger K is, the smaller M is, and the delay of each branch is smaller.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a clock control circuit and method. Background technique [0002] With the continuous evolution of integrated circuit technology, high-speed and low-power circuit design has become more and more mainstream, especially in high-speed circuits such as high-speed IP unit CPU and artificial intelligence processing unit NPU. When ultra-low power consumption is required to save energy. Conventional high-speed circuit design needs to insert a gating clock to reduce power consumption. In the existing timing control circuit, the number of registers loaded by the gating clock is large, and the delay value is large, which may easily lead to an imbalance in the timing path. , so that the timing is not easy to meet the requirements, and the circuit implementation has difficulty in timing convergence, which cannot meet the high-frequency design. Contents of the invention [0003] The in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/04G06F30/3312
CPCG06F1/04
Inventor 夏剑锋
Owner SHENZHEN INTELLIFUSION TECHNOLOGIES CO LTD