Method for semiconductor process and semiconductor structure

Abstract

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer. The invention relates to formation and structure of a contact conductive part.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductors, and more particularly, to methods and semiconductor structures for semiconductor processing. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each of which has smaller and more complex circuits than the previous generation. In IC evolution processes, functional density (eg, the number of interconnected devices per chip area) typically increases while geometry size (eg, the smallest component (or line) that can be created using a fabrication process) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. [0003] As devices scale down, manufacturers have begun to use new and different materials and / or combinations of materials to facilitate dev...

AI Technical Summary

Problems solved by technology

Scaling alone, and in combination with new and different materials, also presents challenges that previous generations of ICs may not have represented in larger geometries

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