LDMOS device and manufacturing method thereof

Abstract

The invention discloses an LDMOS device and a manufacturing method thereof. The LDMOS device includes a source region and a drain region in a substrate and a gate on the substrate laterally between the source region and the drain region. The LDMOS device also includes a field plate in a region between the gate and the drain region on the substrate and a field plate contact on the field plate. Thefield plate contact includes an upper surface including a first portion and a second portion in a longitudinal direction. The upper surface of the field plate contact also electrically contacts a field plate contact metal layer that covers the first portion of the field plate contact and does not cover the second portion of the field plate contact. Thus, the area of the field plate contact metal layer is reduced, the fringe field between the field plate contact metal layer and the drain metal layer is reduced, and the parasitic capacitance between the two is reduced. Therefore, the peak electric field is effectively reduced, or the breakdown voltage of the LDMOS device is effectively improved.

Description

technical field [0001] The present invention relates to a laterally diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) device, in particular to a field plate contact (field plate contact) and a field plate contact metal layer (field plate contact metal layer) of the LDMOS device. Background technique [0002] At present, field plates of various structures are widely used in semiconductor devices to effectively reduce the peak electric field at a given voltage, or to effectively increase the breakdown voltage when the critical electric field is reached. FIG. 1 shows a top view of a partial structure of a conventional LDMOS device 00. Such as figure 1 As shown, the LDMOS device 00 includes a field plate contact 01 over a field plate (not shown) and a field plate contact metal layer 02 over the field plate contact 01 . Wherein, the field plate contact 01 is parallel to the drain contact 03 in the longitudinal direction. A drain contact m...

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Problems solved by technology

[0003] A disadvantage of the above structure is that since the field plate contact metal layer 02 and the drain contact metal layer 04 are parallel, fringing fields will be generated, and the fringing fields make the field plate contact metal layer 02 and the drain contact metal layer 04 A parasitic capacitance is generated between the LDMOS device, which causes the power consumption of the LDMOS device during switching, and its efficiency is reduced

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