Multi-core interaction method and system suitable for nonvolatile memory and storage medium

A non-volatile memory and interactive method technology, applied in the fields of multi-core interactive methods, systems and storage media, can solve the problem of inability to merge I/O requests, the system cannot manage the execution order of I/O requests, and the asymmetry of read and write performance, etc. problem, to achieve the effect of high concurrency, improved stability and high efficiency

Active Publication Date: 2020-02-04
SOUTH CHINA NORMAL UNIVERSITY
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Problems solved by technology

On non-volatile memory devices, in the case of asymmetric read and write performance due to hardware reasons (write performance is significantly lower than read performance), t...

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  • Multi-core interaction method and system suitable for nonvolatile memory and storage medium
  • Multi-core interaction method and system suitable for nonvolatile memory and storage medium
  • Multi-core interaction method and system suitable for nonvolatile memory and storage medium

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Embodiment Construction

[0069] The present invention will be further explained and described below in conjunction with the accompanying drawings and specific embodiments of the description. For the step numbers in the embodiment of the present invention, it is only set for the convenience of explanation and description, and there is no limitation on the order of the steps. The execution order of each step in the embodiment can be carried out according to the understanding of those skilled in the art Adaptive adjustment.

[0070] refer to figure 1 , the embodiment of the present invention provides a multi-core interaction method suitable for non-volatile memory, including the following steps:

[0071] Initialize the interactive request environment through the interactive request submission module, and obtain batch interactive requests;

[0072] Optimize and distribute batch interactive requests through the interactive request scheduling module;

[0073] Assign a kernel thread to each CPU through th...

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Abstract

The invention discloses a multi-core interaction method and system suitable for a nonvolatile memory and a storage medium. The system comprises an interaction request submitting module, an interactionrequest scheduling module, a kernel thread management module, a CPU load detection module and a system crash recovery module. According to the method, an interaction request environment is initialized through an interaction request submitting module, then batch interaction requests are optimized and distributed through an interaction request scheduling module, and then kernel threads are distributed to each CPU through a kernel thread management module. According to the method, batch interaction requests are processed, the advantages of multi-core asynchronous concurrent processing can be brought into full play, the efficiency is high, and the concurrency is high; besides, the load condition of each CPU can be acquired in real time through the CPU load detection module, and the system data can be recovered through the system crash recovery module, so that the stability of the system is improved, and the method and system can be widely applied to the technical field of computers.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a multi-core interaction method, system and storage medium suitable for non-volatile memory. Background technique [0002] Non-volatile memory has the characteristics of byte addressability, high storage density, high-performance read and write, and persistent data storage. In order to take advantage of its byte-addressable and high-speed access characteristics, it is necessary to directly connect non-volatile memory to the memory bus and use it as a persistent memory device. [0003] Traditional volatile storage media, such as mechanical hard disks and solid-state disks, have slow read and write speeds and large-grained reads and writes. The operating system deliberately introduces a multi-level I / O protocol stack at the cost of CPU overhead. Form a variety of read and write optimization strategies in exchange for the improvement of its I / O performance. However, due to the l...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06F9/52
CPCG06F9/505G06F9/5016G06F9/5022G06F9/526
Inventor 李丁丁张新会钟一捷汤庸
Owner SOUTH CHINA NORMAL UNIVERSITY
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