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An off-chip calibration method and system for successive approximation analog-to-digital converters

An analog-to-digital converter, successive approximation technology, applied in analog/digital conversion calibration/test, analog/digital conversion, code conversion, etc., can solve the problems of inability to track ADC errors, complex calibration timing, and calibration circuit occupation, etc. Achieve the effect of increasing overall power consumption, saving wafer area, and high-precision analog-to-digital conversion

Active Publication Date: 2022-04-22
XI AN JIAOTONG UNIV +1
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  • Description
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  • Application Information

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Problems solved by technology

The foreground calibration algorithm means that the ADC will have a separate calibration mode. The switching method of the capacitor array will be different from the subsequent working mode. The calibration process will interrupt the normal operation of the ADC. Although it has the advantage of fast calibration speed, the calibration sequence is more complicated. And it cannot track the error caused by the ADC with environmental changes and device aging and perform continuous calibration
The background calibration algorithm means that when the ADC is working normally, the calibration module will start running at the same time, and there will be no independent calibration mode, which can make the timing of the entire analog-to-digital converter simpler and more unified, but the algorithm is often more complicated, and the comprehensively generated Calibration circuits take up a large die area

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  • An off-chip calibration method and system for successive approximation analog-to-digital converters
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  • An off-chip calibration method and system for successive approximation analog-to-digital converters

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Embodiment Construction

[0047] In order to make the purpose, technical effects and technical solutions of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments It is a part of the embodiment of the present invention. Based on the disclosed embodiments of the present invention, other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall all fall within the protection scope of the present invention.

[0048] see figure 1 , The successive approximation analog-to-digital converter structure mainly includes four parts: a sample-and-hold circuit, an N-bit digital-to-analog converter (DAC) capacitor array, a comparator and a digital logic module. The input signal is sampled and held by the capacitance of the sample-and-hold circ...

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Abstract

The invention discloses an off-chip calibration method and system for successive approximation analog-to-digital converters, comprising the following steps: inputting a sine wave to the ADC to be calibrated; The frequency satisfies the relationship of coherent sampling; the output code value of the comparator of the ADC to be calibrated is collected, and the digital code value of the sine wave is calculated according to the output code value of the comparator; the digital code value of the sine wave obtained through calibration algorithm calibration, Obtain the actual weight of the capacitance array of the ADC to be calibrated, write the actual weight of the capacitance array into the weight register of the ADC to be calibrated, and complete the calibration; in the calibration algorithm, the capacitance weight is measured by the SNR of the ADC to be calibrated degree of mismatch. The present invention can achieve high-precision analog-to-digital conversion by calculating and adjusting capacitance weights without affecting the normal working mode of the ADC and without additional function configuration.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, in particular to an off-chip calibration method and system for successive approximation analog-to-digital converters. Background technique [0002] Today's rapid development of semiconductor technology has made rapid progress in the computing power, power consumption, and speed of digital chips, but the progress of the entire system is inseparable from the support of high-speed and high-precision digital-to-analog converters (ADCs). In recent years, ADC research has also been developing rapidly. ADCs with various architectures have emerged, each with their own strengths in accuracy, power consumption, and speed. Among them, the more balanced successive approximation analog-to-digital converter (SAR) ADC) has become the first choice in many fields including industrial control and medical devices. However, in the direction of high-precision development, due to the deviation of...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
CPCH03M1/1009
Inventor 王红义陈晨张海峰刘沛张国和梁峰
Owner XI AN JIAOTONG UNIV