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Photosensitive chip packaging structure

A packaging structure, photosensitive chip technology, applied in radiation control devices, electrical components, electric solid devices, etc., can solve the problems of easy external interference of image acquisition, poor information image acquisition effect, etc., and achieve good collection effect

Inactive Publication Date: 2020-02-11
安徽国晶微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Wafer-level chip size packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging testing, and substrate manufacturing. It is a hot spot in the current packaging field and a future development trend. The acquisition effect is not good, and the image acquisition is vulnerable to external interference

Method used

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Embodiment Construction

[0025] The present invention is described in further detail now in conjunction with accompanying drawing. These drawings are all simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, so they only show the configurations related to the present invention.

[0026] Examples of the described embodiments are shown in the drawings, wherein like or similar reference numerals designate like or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0027] In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer"...

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Abstract

The invention discloses a photosensitive chip packaging structure, which comprises a photosensitive element, a hollow wall, a cavity and a substrate, wherein a first surface and a second surface are respectively arranged on two sides of the substrate; one surface of the photosensitive element is provided with a photosensitive area, the other surface of the photosensitive element is provided with abottom plate; the photosensitive area is provided with the hollow wall and the cavity side by side; the lower part of the photosensitive area is electrically connected with a welding pad; the weldingpad is used for electrically connecting an internal circuit structure of the photosensitive element with an external convex block through a ceramic layer and a connecting layer; a thin film is arranged at the joint of the cavity and the second surface; nanotextures are arranged on the thin film; and a lens is arranged in the cavity. Compared with the prior art, as multiple films are arranged, image information can be better collected, the bottom plate is wrapped with the protection layer for preventing electromagnetic interference, and the protection layer can protect the internal circuit ofthe photosensitive element against interference of external electromagnetism during collection.

Description

technical field [0001] The invention relates to the technical field of photosensitive chip packaging, in particular to a photosensitive chip packaging structure. Background technique [0002] The photosensitive element is the core of a digital camera, and it is also the most critical technology. The development path of digital cameras can be said to be the development path of photosensitive components. There are two core imaging components of a digital camera: one is the widely used CCD (charge coupled) element; the other is a CMOS (complementary metal oxide semiconductor) device. Compared with traditional cameras, traditional cameras use "film" as their carrier for recording information, while the "film" of digital cameras is their imaging photosensitive element. [0003] The existing wafer-level chip size packaging technology is a technology that performs packaging and testing on the entire wafer and then cuts a single finished chip. The size of the packaged chip is exac...

Claims

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Application Information

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IPC IPC(8): H01L23/552H01L27/146H01L27/148
CPCH01L23/552H01L27/14618H01L27/14625H01L27/14634H01L27/14806
Inventor 庞士德阮怀其
Owner 安徽国晶微电子有限公司
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