Data latch circuit and pulse signal generator thereof

Abstract

A data latch circuit and a pulse signal generator thereof are provided. The pulse signal generator includes a first buffer, a second buffer, a pull-up switch and an output buffer. The first buffer generates a first buffering signal according to an input signal and a feedback signal. The second buffer generates a second buffering signal according to the input signal and the first buffering signal.The pull-up switch pulls up the second buffering signal according to the first buffering signal. The output buffer generates at least one output pulse signal according to the second buffering signal.The output buffer further outputs the at least one output pulse signal to the first buffer to be the feedback signal.

Description

technical field [0001] The present invention relates to a data latch circuit and its pulse signal generator, and in particular to a fast-acting data latch circuit and its pulse signal generator. Background technique [0002] Regarding the design of the data latch circuit, in the conventional technical field, it is common to use a static flip-flop (static flip-flop), a dynamic flip-flop (dynamic flip-flop) and a pulse latch flipflop (pulse latch flipflop). ) to construct. In the conventional technical field, although the static flip-flop has a relatively robust effect on the noise margin, it usually requires a larger circuit area to be configured, resulting in increased cost. However, the conventional dynamic flip-flops are prone to data leakage due to the phenomenon of leakage current, and the conventional dynamic flip-flops also often cause malfunctions due to signal surges. However, the design of the pulse latch flip-flop requires a relatively high area density, and the ...

AI Technical Summary

Problems solved by technology

In the conventional technical field, although the static flip-flop has a relatively robust effect on the noise margin, it often requires a larger circuit area to be configured, resulting in increased cost

However, the dynamic flip-flops of the conventional technology are prone to data leakage due to the phenomenon of leakage current, and the dynamic flip-flops of the conventional technology also often cause malfunctions due to signal surges.

The design of the pulse latch flip-flop requires a relatively high area density, which is more difficult in circuit layout.

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