Integral module integration input system realized by field-programmable gate array

Abstract

The invention discloses an integral module integration input system realized by a field-programmable gate array. The system comprises an analog-to-digital conversion module, a processing module, a data control module, a register module, a user datagram protocol module and a gigabit internet access module. A user can select a three-wire type or four-wire type serial port interface to allow programming and readback of many internal parameters. Advanced low-spurious and distortion design technology is provided, high-quality synthesis of broadband signals from a baseband to a high-intermediate frequency can be realized, and system design is enabled to be more flexible.

Description

technical field [0001] The invention relates to the field of protocol standards of converters, in particular to a field programmable gate array to realize the integrated input system of the whole module. Background technique [0002] In the past, most analog-to-digital converters (Analog To Digital Converter, hereinafter referred to as DAC) did not configure high-speed serial interfaces, that is, Field Programmable Gate Arrays (Field Programmable Gate Array, hereinafter referred to as FPGA) and converters did not rely on any Common standard interface to take advantage of high-speed Serializer / Deserializer bandwidth. For most signal processing systems, the primary defining system is analog or RF frequency, dynamic range, and sampling rate to establish converter selection criteria. A converter is a device that converts one signal into another. In automatic instrumentation equipment and automatic control systems, one signal is often converted into another signal compared with...

AI Technical Summary

Problems solved by technology

In previous UDP modules, the frame clock was the absolute time reference for the system, and the frame clock and the converter sample clock were usually the same, so there was not enough flexibility, and when routing the same signal to multiple devices and count the skew between different routing paths, it introduces unnecessary complexity to the system design

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