Structure and method for realizing receiving synchronization of multiple RapidIO test board cards and test equipment

Abstract

The invention provides a structure and method for realizing receiving synchronization of multiple RapidIO test board cards and test equipment. The test board comprises a backboard and a plurality of cascaded RapidIO test board cards, wherein each RapidIO test board card is provided with a synchronous clock output interface, a synchronous clock input interface, a synchronous clock generation deviceand a clock selector, and the synchronous clock input interface of each RapidIO test board card is connected with the synchronous clock output interface of the previous RapidIO test board card; the input end of each RapidIO test board card clock selector is respectively connected with the synchronous clock generation device and the synchronous clock input interface of the RapidIO test board card;and the clock selector is used for selecting a clock signal of the RapidIO test board card and transmitting the clock signal to the next RapidIO test board card. A GPS timing system module does not need to be used, hardware circuits among the multiple RapidIO test board cards are the same in composition, master and slave modes are switched through a dial switch, signal synchronization of the multiple board cards can be achieved from hardware operation, multiplexing and cascading of the multiple board cards are achieved, use is easy and convenient, and implementation is easy.

Description

technical field [0001] The present disclosure relates to the technical field related to testing technology, and in particular, relates to a method for realizing synchronization of reception of multiple RapidIO test boards and automatic testing equipment. Background technique [0002] The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art. [0003] With the development of the RapidIO bus, the transmission rate continues to increase, and the maximum test rate of a single channel reaches 6.25Gb / s, and the maximum support for 4x mode. However, in the actual test process, the test bandwidth of a single test board is still insufficient, and multiple RapidIO test boards are required to be tested in parallel, which involves time synchronization when multiple RapidIO test boards receive data. [0004] In the prior art, a method of adding a GPS time system module may be adopted, and the GPS t...

AI Technical Summary

Problems solved by technology

The inventors found that the existing technology adopts the mode of GPS time system module. On the one hand, the structure of GPS time system module is in the form of a board card, which needs to occupy a card slot separately, which takes up space and increases weight; on the other hand, GPS time system module Only used to provide synchronous clock signal, low cost performance

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