[0030] In order to clearly illustrate the technical features of the solution, the present invention will be described in detail below through specific embodiments and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted from the present invention to avoid unnecessarily limiting the present invention.
[0031] like figure 1 As shown, it is a block diagram of the circuit structure of the embodiment of the present invention. The circuit includes a control unit, a locking and unlocking unit, a voltage dividing unit and a protection unit. The control unit is connected to the locking and unlocking unit and the voltage dividing unit, and the protection unit is connected to the locking and unlocking unit. The control unit is used to output a high level when the circuit detects the first high-frequency narrow pulse signal, output a low level when the circuit detects the second high-frequency narrow pulse signal, and the locking and unlocking unit is used to lock the first high-frequency narrow pulse signal or unlocking the first high-frequency narrow pulse signal, the voltage dividing unit is used to provide voltage dividing for the locking and unlocking unit, and the protection unit is used for overvoltage protection.
[0032] like figure 2 As shown, it is a circuit schematic diagram of an embodiment of the present invention.
[0033] The control unit includes a P-type MOSFET transistor Q1, a resistor R1 and a resistor R2, the gate of the P-type MOSFET transistor Q1 is connected to one end of the resistor R1 and one end of the resistor R2, and the source of the P-type MOSFET transistor Q1 is connected to the other end of the resistor R1 and Vcc , the drain of the P-type MOSFET transistor Q1 is connected to the output voltage Vout and one end of the resistor R6.
[0034] In the embodiment of the present invention, the type of the P-type MOSFET transistor Q1 is IRFR5305, the absolute value of the rated voltage of VGS is less than 5V, and other PMOS transistors that meet this requirement can also be used.
[0035] The locking and unlocking unit includes an NPN transistor Q2, a resistor R3, a resistor R6, a capacitor C1 and a capacitor C2. The collector of the NPN transistor Q2 is connected to the other end of the resistor R2 and one end of the capacitor C1, and the base of the NPN transistor Q2 is connected to one end of the capacitor C2 and One end of the resistor R5, the emitter of the NPN transistor Q2 is grounded, the other end of the capacitor C2 is connected to one end of the resistor R3 and the other end of the resistor R6, and the other end of the resistor R3 is connected to the other end of the capacitor C1.
[0036] In the embodiment of the present invention, the model of the NPN transistor Q2 is S8050 (the turn-on voltage is 0.7V). In the schematic diagram of this embodiment, the base voltage of Q2 is about 0.9V, and other low-power transistors that meet the turn-on voltage of less than 0.9V , can be used.
[0037] The voltage dividing unit includes a resistor R4, one end of the resistor R4 is connected to Vout, the other end of the resistor R4 is connected to one end of the resistor R5 and one end of the capacitor C2, and the other end of the resistor R5 is grounded; the resistor R4 and the resistor R5 are connected in series, and the resistor R5 is used to supply the NPN The base of transistor Q2 provides the second divided voltage.
[0038] The protection unit includes a voltage regulator tube ZD1 and a resistor R7. The positive electrode of the voltage regulator tube ZD1 is connected to one end of the resistor R7 and one end of the capacitor C1. The negative electrode of the voltage regulator tube ZD1 is connected to the other end of the capacitor C1 and the positive input end of the high-frequency narrow pulse. The other end of the resistor R7 is connected to the negative input end of the high-frequency narrow pulse; the Zener tube ZD1 is used for overvoltage protection to prevent the noise voltage from being too large and damaging the subsequent components, and the resistor R7 is used for current limiting.
[0039] The voltage regulator tube ZD1 used in the embodiment of the present invention is IN4733, the voltage regulator value is 5.1V, and the voltage regulator value is less than the rated value of the capacitor C1. Other voltage regulator tubes that meet this requirement can also be selected.
[0040] The working principle of the circuit of the embodiment of the present invention is:
[0041] When the circuit is powered on and no high-frequency narrow pulse signal is detected, the VGS of the P-type MOSFET transistor Q1 does not reach the turn-on voltage, the P-type MOSFET transistor Q1 is turned off, the base of the NPN transistor Q2 is turned off without voltage division, and the output voltage Vout output low level;
[0042] When the circuit detects the first high-frequency narrow pulse signal, the capacitor C1 is turned on instantly, and then, C2 is also quickly turned on. The capacitor C1 and the capacitor C2 are equivalent to a wire. The power supply Vcc passes through the resistor R1, the resistor R2, and the capacitor C1. , resistor R3, capacitor C2, and resistor R5 are turned on, the base of NPN transistor Q2 gets the first voltage divider, and NPN transistor Q2 is instantly turned on. At this time, the gate voltage of P-type MOSFET transistor Q1 becomes 0, P-type The MOSFET Q1 is turned on instantly, and the output voltage Vout outputs a high level. At this time, the resistor R4 and the resistor R5 are connected in parallel. The resistor R5 provides a second voltage divider for the base of the NPN transistor Q2, and the NPN transistor Q2 and the P-type MOSFET transistor Q1 maintain conduction. In the on state, the output voltage Vout continues to output a high level, that is, the first high-frequency narrow pulse signal is locked;
[0043] When the circuit detects the second high-frequency narrow pulse signal, the second divided voltage of the base of the NPN transistor Q2 is rapidly discharged through the collector of the NPN transistor Q2, the capacitor C1, the resistor R3 and the capacitor C2, and the base of the NPN transistor Q2 is rapidly discharged. The voltage drop is cut off instantly, the gate voltage of the P-type MOSFET transistor Q1 is restored to Vcc, the P-type MOSFET transistor Q1 is turned off, and the output voltage Vout continues to output a low level, that is, the first high-frequency narrow pulse signal is unlocked.
[0044] like image 3 As shown, it is a flowchart of the method according to the embodiment of the present invention, which specifically includes:
[0045] When the circuit is powered on and no high-frequency narrow pulse signal is detected, the P-type MOSFET transistor Q1 and the NPN transistor Q2 are turned off, and the output voltage Vout outputs a low level;
[0046] When the circuit detects the first high frequency narrow pulse signal, the first high frequency narrow pulse signal is locked;
[0047] When the circuit detects the second high frequency narrow pulse signal, the first high frequency narrow pulse signal is unlocked.
[0048] The process of locking the first high-frequency narrow pulse signal is as follows:
[0049] When the circuit detects the first high-frequency narrow pulse signal, the capacitor C1 is turned on instantly, and then, C2 is also quickly turned on. The capacitor C1 and the capacitor C2 are equivalent to a wire. The power supply Vcc passes through the resistor R1, the resistor R2, and the capacitor C1. , resistor R3, capacitor C2, and resistor R5 are turned on, the base of NPN transistor Q2 gets the first voltage divider, and NPN transistor Q2 is instantly turned on. At this time, the gate voltage of P-type MOSFET transistor Q1 becomes 0, P-type The MOSFET Q1 is turned on instantly, and the output voltage Vout outputs a high level. At this time, the resistor R4 and the resistor R5 are connected in parallel. The resistor R5 provides a second voltage divider for the base of the NPN transistor Q2, and the NPN transistor Q2 and the P-type MOSFET transistor Q1 maintain conduction. In the on state, the output voltage Vout continues to output a high level.
[0050] The process of unlocking the first high-frequency narrow pulse signal is as follows:
[0051] When the circuit detects the second high-frequency narrow pulse signal, the second divided voltage of the base of the NPN transistor Q2 is rapidly discharged through the collector of the NPN transistor Q2, the capacitor C1, the resistor R3 and the capacitor C2, and the base of the NPN transistor Q2 is rapidly discharged. The voltage drop is cut off instantly, the gate voltage of the P-type MOSFET transistor Q1 is restored to Vcc, the P-type MOSFET transistor Q1 is turned off, and the output voltage Vout continues to output a low level.
[0052] If multiple groups of high-frequency narrow pulse signals are detected during the operation of the circuit, the process of locking and unlocking the high-frequency narrow pulse signals will be repeated until the circuit stops working.
[0053] The above are only the preferred embodiments of the present invention. For those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made, and these improvements and modifications are also regarded as the present invention. The scope of protection of the invention.
