Forming method for semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as mutual interference, affecting device performance and stability, and achieve the effect of avoiding mutual interference, improving performance and stability, and being easy to receive.

Active Publication Date: 2020-03-10
CHANGXIN MEMORY TECH INC
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AI-Extracted Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a method for forming a semiconductor device to solve the problem ...
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Method used

[0037] The specific embodiments of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will be more apparent from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0040] In a preferred solution, the top surface of the gate conductive layer 33 is lower than the top surface of the substrate 1, that is, the top surface of the gate conductive layer 33 is lower than the drain region 25 and the The top boundary of the source region 24. In this way, the overlapping area of ​​the gate conductive layer 33 and the drain region 25 and the source region 24 can be reduced, thereby effectively improving the phenomenon of junction current generated by electric field changes. When the top surface of the gate conductive layer 33 is lower than the top surface of the substrate 1, it is equivalent to that the top of the gate conductive layer 33 is lower than the opening of the gate trench 31 (or can It is regarded as the opening of ...
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Abstract

The invention provides a forming method for a semiconductor device. Firstly, a plurality of gate structures are formed in a substrate; each gate structure is formed between a drain region and a sourceregion, and a plurality of access transistors are formed; the adjacent access transistors in the same active region share the drain region; twice ion implantation are carried out so as to enable thebottom of the drain region to sink to each source region; when the access transistors are used, electrons flow to the drain regions from the source regions, and the bottoms of the drain regions more sink to the source regions, so that the drain regions receive the electrons more easily, mutual interference caused by stray current formed between the two access transistors is avoided, and the performance and stability of the device are improved.

Application Domain

TransistorSemiconductor/solid-state device manufacturing

Technology Topic

Device materialMaterials science +6

Image

  • Forming method for semiconductor device
  • Forming method for semiconductor device
  • Forming method for semiconductor device

Examples

  • Experimental program(1)

Example Embodiment

[0035] There is a semiconductor device such as figure 1 As shown, it includes a substrate 1' and two gate structures 3', a drain region 25' and a plurality of source regions 24' are formed in the substrate 1, and the source regions 24' conform to the active region The extension direction is arranged on both sides of the drain region 25', and each gate structure 3' is formed in the substrate between the drain region 25' and the source region 24' to form an access transistors, the adjacent access transistors in the same active region share the drain region 25', and the drain region 25' and the source region 24' extend downward from the surface of the substrate 1' to the same depth , forming a symmetrical structure. It can be understood that, when this semiconductor device is in use, the part of the substrate 1' along the bottom of the gate structure 3' constitutes a channel region, and when an access transistor is turned on, its source region 24' When the electrons migrate to the drain region 25' along the channel region, because the distance between the two access transistors in the same active region is relatively close, the electrons migrate to the drain region 25'. The distance is about the same as the distance to the channel region of the adjacent access transistors, so stray currents are easy to form, causing the adjacent access transistors to interfere with each other and affect the performance of the device.
[0036] Based on this, the present invention provides a method for forming a semiconductor device. First, a plurality of gate structures are formed in a substrate, and each gate structure is formed between a drain region and a source region to form a plurality of access transistors. , and the adjacent access transistors in the same active region share the drain region, perform ion implantation twice so that the bottom of the drain region sinks further into each of the source regions, when the When the access transistor is in use, electrons flow from the source region to the drain region, and since the bottom of the drain region sinks further below each of the source regions, the drain region is more likely to receive electrons, avoiding Stray currents are formed between the two access transistors to interfere with each other, which improves the performance and stability of the device.
[0037] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. The advantages and features of the present invention will be more apparent from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0038] see Figure 14 , the present embodiment provides a semiconductor device, comprising: a substrate 1 having a plurality of active regions in the substrate 1, a drain region 25 and a plurality of source regions are formed in the substrate of the active region 24, a plurality of the source regions are arranged on both sides of the drain region 25 along the extending direction of the active region, and the bottom of the drain region 25 is further sunk below each of the source regions 24; and, A plurality of gate structures 3 are formed in the active region of the substrate 1 and located between the drain region 25 and the source region 24 to form a plurality of access transistors, and in the same active region The drain regions 25 of the adjacent access transistors in the source region are shared.
[0039] see Figure 7 and Figure 14 , a plurality of gate trenches 31 are formed in the substrate 1 in the active region, and each of the gate structures 3 is formed in the gate trenches 31, wherein the gate structures 3 include Gate dielectric layer 32 and gate conductive layer 33, the gate trench 31 is formed in the substrate 1 and located between the drain region 25 and the source region 24, wherein the drain region 25 and the source region 24 are both close to the opening of the gate trench 31, and the side boundaries of the drain region 25 and the source region 24 both extend to the side walls of the gate trench 31 close to the opening . The gate dielectric layer 32 covers the bottom wall and the sidewall of the gate trench 31 , and the gate conductive layer 33 is filled in the gate trench 31 .
[0040]In a preferred solution, the top surface of the gate conductive layer 33 is lower than the top surface of the substrate 1, that is, the top surface of the gate conductive layer 33 is lower than the drain region 25 and the source region 24 top border of the . In this way, the overlapping area of ​​the gate conductive layer 33 and the drain region 25 and the source region 24 can be reduced, thereby effectively improving the phenomenon of junction current generated by electric field changes. When the top surface of the gate conductive layer 33 is lower than the top surface of the substrate 1, it is equivalent to that the top of the gate conductive layer 33 is lower than the opening of the gate trench 31 (or can It is regarded as the opening of the gate trench), so as to form an accommodating space in the gate trench 31 and above the gate conductive layer 33 . Optionally, an insulating layer 34 is filled in the accommodating space of the gate trench 31 to cover the gate conductive layer 33, that is, using the accommodating space of the gate trench 31 The space can not only better isolate and protect the gate conductive layer 33 (for example, it can avoid the problem that the gate conductive layer 33 is partially exposed due to the displacement deviation of the insulating layer 34); The insulating layer 34 can be formed in a self-aligned manner, which is beneficial to simplify the manufacturing process.
[0041] Further, please continue to Figure 14 , the gate structure 3 is located between the drain region 25 and the source region 24 to form an access transistor. It can be understood that the adjacent access transistors in the same active region respectively use the adjacent one The source region 24 shares the drain region 25 . The drain region 25 and the source region 24 respectively extend from the top surface of the substrate 1 to the inside of the substrate 1 to a first depth position of the substrate 1 (from the top surface of the substrate 1 The first depth value to the first depth position is H1) and the second depth position (the second depth value from the top surface of the substrate 1 to the second depth position is H2), the gate The bottom of the structure is located at a third depth position of the substrate 1 (the third depth value from the top surface of the substrate 1 to the third depth position is H3), and the first depth position is lower than The second depth position (the first depth value H1 is greater than the second depth value H2), so that the bottom of the drain region 25 sinks further below the source region, and the third depth position of the gate structure 3 is lower At the first depth position of the drain region 25 (the third depth value H3 is greater than the first depth value H1), the bottom of the gate trench 31 is further sunk in the drain region 25 and the source region 24 , to form the channel region of the access transistor, that is, the region from the drain region 25 to the source region 24 along the trench sidewall and trench bottom wall of the gate trench 31 . When a storage transistor is in use, electrons in its source region 24 migrate to its drain region 25 along the channel region, since the drain region 25 sinks further in the source region 24, the drain region 25 is easier to receive electrons in the channel region, which can prevent electrons from forming stray currents between adjacent access transistors and interfering with each other, improving the performance and stability of the device.
[0042] Further, continue to refer to Figure 14 As shown, a well region 2 is also formed in the substrate 1, the drain region 25 and the source region 24 are both formed in the well region 2, and the ion doping concentration in the well region 2 is lower than The ion doping concentration in the drain region 25 and the source region 24. Further, the doping type of the well region 2 can be determined according to the type of transistor formed, for example, when the transistor is an N-type transistor, the well region 2 can be correspondingly doped with boron ions (B); When the transistor is a P-type transistor, the well region 2 can be correspondingly doped with phosphorous ions (P).
[0043] In addition, an isolation layer (not shown) is formed on the substrate 1, and the isolation layer covers the top surface of the substrate corresponding to the drain region 25 and the source region 24, so as to prevent the drain region from 25 and the source region 24 are exposed from the top surface of the substrate 1, so that the drain region 25 and the source region 24 can be isolated and protected, preventing the drain region 25 and the source region from being damaged in the subsequent process. 24 for damage.
[0044] Based on this, if figure 2 As shown, the present embodiment provides a method for forming a semiconductor device, including:
[0045] S1: provide a substrate, the substrate has a plurality of active regions, a first region for forming a drain region and a plurality of second regions for forming a source region are defined in the active region, and a plurality of The second region is arranged on both sides of the first region along the extending direction of the active region;
[0046] S2: forming a plurality of gate structures in the substrate, and using the gate structures to separate the first region and the second region;
[0047] S3: forming a drain region and a source region in the first region and the second region, the bottom of the drain region is further sunk in each of the source regions, and the gate structure is located in the drain region and the second region. A plurality of access transistors are formed between the source regions, and the drain regions of the adjacent access transistors in the same active region are shared.
[0048] Specifically, see image 3 , providing a substrate 1, the substrate 1 has a first region 21 for forming a drain region and a plurality of second regions 22 for forming a source region, and the first regions 21 are located at two adjacent between the second regions 22. Further, a well region 2 is formed in the substrate 1 , and a drain region and a source region to be formed subsequently are both formed in the well region 2 . The drain region and the source region can be formed before or after the gate structure is formed. In this embodiment, the gate structure is formed first, and then the drain region and the source region are formed as an example for illustration.
[0049] read on image 3 , first forming two gate trenches 31 in the substrate 1, and using each of the gate trenches 31 to separate the first region 21 and the second region 22, and then as Figure 4 As shown, a thermal oxidation process is performed to form a gate dielectric layer 32 in the gate trench 31, and the gate dielectric layer 32 covers the sidewall and bottom wall of the gate trench; next, refer to Figure 5-Figure 6 , forming a conductive material layer 4 on the substrate 1, the conductive material layer 4 covers the substrate 1 and fills the gate trench 31, and performs an etch-back process on the conductive material layer 4, removing the portion of the conductive material layer 4 that covers the substrate 1, and retaining the portion of the conductive material layer 4 that fills the gate trench 31 to form the gate conductive layer 33, in a preferred solution , in the etch-back process of the conductive material layer 4, after removing the part of the conductive material layer 4 covering the substrate 1, the conductive material layer 4 filled in the gate trench 31 can be further performed etch back process to reduce the height of the conductive material layer 4 . In this way, the top of the finally formed gate conductive layer 33 can be made lower than the opening of the gate trench 31, so that an accommodating space can be formed in the gate trench 31 and located in the gate trench 31. above the gate conductive layer 33; then as Figure 7 As shown, an insulating layer 34 is filled in the accommodating space of the gate trench 31 to cover the gate conductive layer 33, that is, the insulating layer 34 can be self-aligned and filled in the In the accommodating space, the insulating layer 34 can be used to isolate and protect the gate conductive layer 33 .
[0050] Further, after the gate structure 3 is formed, an asymmetric drain region and a source region need to be formed next. The drain region and the source region can be formed by performing two ion implantation processes, and there are many specific ways, and the following two ways are only schematically introduced.
[0051] like Figure 8-Figure 10 and Figure 14 As shown, it is a method of forming drain and source regions. like Figure 8 As shown, the first ion implantation process is first performed, and ion implantation is performed on the substrates of the first region 21 and the second region 22 at the same time, so as to form the first ion implantation process in the first region 21 and the second region 22. A first doped region 23 of conductivity type, the first doped region 23 extends from the top surface of the substrate 1 to the inside of the substrate 1 to a second depth position, at this time the first doped region 23 in the substrate 1 should not be too deep (the first doped region 23 located in the second region 22 constitutes the source region 24), so as to leave a margin for the second ion implantation process , and the depths of the first doped regions 23 in the first region 21 and the second region 22 are the same.
[0052] Then as Figure 9 As shown, a second mask layer 51 is formed on the substrate 1, the second mask layer 51 covers the substrate 1 corresponding to the second region 22 and the gate structure 3, and the An opening corresponding to the first region 21 is formed in the second mask layer 51, and then a second ion implantation process is performed on the substrate of the first region 21 using the second mask layer 51 as a mask, Ion implantation is performed in the first region 21 to a region of a set depth downward from the bottom of the first doped region 23 to form a second doped region below the first doped region 23 . The capability of the second ion implantation process is greater than the energy of the first ion implantation process, so that the ion implantation depth of the second ion implantation process is larger, and the conductivity type of the impurity ions implanted by the second ion implantation process The conductivity type of the impurity ions implanted in the first ion implantation process is the same, so that the conductivity types of the first doped region 23 and the second doped region are the same.
[0053] Next as Figure 10 As shown, using the second mask layer 51 as a mask, a bit line contact 61 is formed on the substrate 1 of the drain region 25, and the bit line contact 61 is used to connect to the bit line of the semiconductor device. , that is, the second mask layer 51 is directly used to form the mask layer for forming the bit line contact 61, and no additional mask layer is required, so that a photomask can be omitted, or, compared to the prior art In this embodiment, when realizing the asymmetrical source and drain regions, no additional photomask is needed. Finally, the second mask layer 51 is peeled off to form a storage capacitor contact 62 on the substrate 1 of the source region 24, forming as Figure 14 In the semiconductor device shown, the second doped region in the first region 21 is connected to the first doped region 23 to form the drain region 25, and the first doped region in the second region 22 23 constitutes the source region 24, specifically as Figure 14 shown. It can be understood that, since the first region 21 has performed two ion implantation processes, the depth of the doped region in the first region 21 is increased, so that the formed drain region 25 is formed in the substrate 1 The further sinks in the source region 24 .
[0054] like Figure 11-Figure 14 As shown, it is another method of forming drain and source regions. Firstly, a first ion implantation process is performed on the substrate 1 to form a first doped region 23 of a first conductivity type in the first region 21 and the second region 22, and the first doped region 23 is formed from the first doped region 23. The top surface of the substrate 1 extends to the inside of the substrate 1 to a first depth position. Unlike the above method, the depth of the first doped region 23 in the substrate 1 needs to be deeper at this time. (The first doped region 23 located in the first region 21 constitutes the drain region 25 ), and the depths of the doped regions 23 in the first region 21 and the second region 22 are the same.
[0055] Then as Figure 12 As shown, a first mask layer 52 is formed on the substrate 1, the first mask layer 52 covers the substrate 1 corresponding to the first region 21 and the gate structure 3, and the An opening corresponding to the second region 22 is formed in the first mask layer 52, and then using the first mask layer 52 as a mask, a second ion implantation process is performed on the second region 22, and the The bottom of the first doped region 23 in the second region 22 is implanted with ions of the second conductivity type into the region of the set depth downward, forming a second doped region of the second conductivity type in the second region. In the first doped region 23 . The capability of the second ion implantation process is greater than the energy of the first ion implantation process, so that the ion implantation depth of the second ion implantation process is larger, and the conductivity type of the impurity ions implanted by the second ion implantation process Contrary to the conductivity type of the impurity ions implanted by the first ion implantation process, the second doped region of the second conductivity type extends from the bottom boundary of the first doped region 23 to the surface of the substrate 1 extending to between the second depth positions (the doping type of the second doped region is the same as that of the well region 2 at this time).
[0056]Further, when performing the second ion implantation process, the second depth position of the bottom of the source region 24 can be controlled by controlling the ion implantation depth of the second ion implantation process, so as to adaptively adjust the depth of the channel region. The length, for example, when the second depth value H2 becomes smaller, the length of the channel region becomes longer; on the contrary, when the second depth value H2 becomes larger, the length of the channel region becomes shorter. Of course, in this embodiment, the size of the first depth value H1 can also be controlled accordingly, or the sizes of the first depth value H1 and the second depth value H2 can be controlled simultaneously to adjust the length of the channel region.
[0057] Next as Figure 13 As shown, using the first mask layer 52 as a mask, a storage capacitor contact 62 is formed on the substrate 1 of the source region 24, and the storage capacitor contact 62 is used to connect with the storage capacitor of the semiconductor device , that is, the first mask layer 52 is directly used to form the mask layer for forming the storage capacitor contact 62, and no additional mask layer is needed, or it can also be understood that this embodiment achieves an asymmetric source In the case of the drain area, no additional mask is required. Finally, the first mask layer 52 is peeled off to form a bit line contact 61 on the substrate 1 of the drain region 25, forming as Figure 14 In the semiconductor device shown, the first doped region 23 in the first region 21 constitutes the drain region 25, and the first doped region 23 in the second region 22 extracts from the second The portion from the depth position to the surface of the substrate 1 constitutes the source region 24 of the first conductivity type. It can be understood that, since the second region 22 has performed two ion implantation processes, the depth of the first doped region 23 in the second region 22 is reduced, so that the formed drain region 25 is formed in the The depth in the substrate 1 is lower than the source region 24 .
[0058] To sum up, in the method for forming a semiconductor device provided by the embodiment of the present invention, firstly, a plurality of gate structures are formed in the substrate, and each of the gate structures is formed between the drain region and the source region to form a plurality of memory structures. access transistors, and the adjacent access transistors in the same active region share the drain region, perform ion implantation twice so that the bottom of the drain region sinks further into each of the source regions, When the access transistor is in use, electrons flow from the source region to the drain region, since the bottom of the drain region sinks further into each of the source regions, making it easier for the drain region to receive electrons, The mutual interference caused by the formation of stray currents between the two access transistors is avoided, and the performance and stability of the device are improved.
[0059] The foregoing are only preferred embodiments of the present invention, and do not limit the present invention in any way. Any person skilled in the technical field, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the technical solution of the present invention. The content still belongs to the protection scope of the present invention.

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