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ESD/EOS protection method based on substrate-assisted triggering and voltage clamping

A voltage clamping, substrate-assisted technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of single protection direction and poor ESD robustness, reduce the trigger voltage, improve the conduction uniformity, weaken the The effect of current heat accumulation effect

Active Publication Date: 2021-12-03
JIANGNAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For the problems of easy latch-up, poor ESD robustness per unit area and single protection direction in traditional ESD / EOS protection solutions

Method used

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  • ESD/EOS protection method based on substrate-assisted triggering and voltage clamping
  • ESD/EOS protection method based on substrate-assisted triggering and voltage clamping
  • ESD/EOS protection method based on substrate-assisted triggering and voltage clamping

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Embodiment 1

[0036] This embodiment proposes an ESD / EOS protection method of substrate-assisted triggering and voltage clamping, which is realized by an ESD / EOS protection device of substrate-assisted triggering and voltage clamping. By utilizing the strong ESD robustness of the SCR structure and the characteristics of the MOS auxiliary trigger path, combined with the multiple device structures of SCR, MOS and Zener diodes, the low-voltage trigger and immune latch-up characteristics can be achieved through a composite design, and, by combining the MOS The gate of the gate is connected to the substrate resistor, and the substrate leakage current can provide a weak potential for the polysilicon gate of the MOS, and the auxiliary circuit is quickly turned on. In addition, the fully symmetrical device structure enables the device to achieve bi-directional ESD protection or anti-surge function.

[0037] The three-dimensional structure of the protective device is as figure 1 As shown, including...

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Abstract

The invention discloses an ESD / EOS protection method for substrate auxiliary triggering and voltage clamping, belonging to the field of electrostatic discharge protection and anti-surge of integrated circuits. The ESD / EOS protection device with substrate auxiliary triggering and voltage clamping provided by the invention can be used to improve the anti-ESD / EOS ability of integrated circuits. The application circuit unit of the method of the present invention is mainly composed of a P substrate, a first N well, a second N well, a P well, a first P+ implantation region, a second P+ implantation region, a third P+ implantation region, a fourth P+ implantation region, The fourth P+ implantation region, the fifth P+ implantation region, the sixth P+ implantation region, the first N+ implantation region, the second N+ implantation region, the third N+ implantation region, the fourth N+ implantation region, the fifth N+ implantation region, the sixth It consists of N+ injection region, polysilicon gate and its covered thin gate oxide layer, and metal lines. The invention can reduce the trigger voltage, improve the fast opening speed, enhance the ESD robustness, avoid the latch effect and enhance the protection efficiency per unit area.

Description

technical field [0001] The invention belongs to the field of electrostatic discharge protection and anti-surge of integrated circuits, relates to an ESD protection or anti-surge circuit, and in particular to an ESD / EOS protection method of substrate auxiliary triggering and voltage clamping. Background technique [0002] With the development of semiconductor technology, the degree of circuit integration continues to expand, and the electrical performance is also continuously improved. However, the expansion of integration has led to the continuous shrinking of process size, which has led to increasingly prominent reliability problems of integrated circuits (IC) and electronic products, mainly manifested in obvious process fluctuations and increased power consumption per unit area. Therefore, the electrostatic discharge (ESD) and electrostatic overstress (EOS) protection capabilities of ICs and electronic products are weakened, which has become a major factor for system failu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0255H01L27/0266H01L27/0296
Inventor 梁海莲冯希昆顾晓峰
Owner JIANGNAN UNIV
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