Constant slope digital-to-time converter and control method thereof

Abstract

The invention discloses a constant slope digital-to-time converter and a control method thereof, and the constant slope digital-to-time converter comprises a discharge load capacitor which is used forstoring charges so as to discharge and generate a voltage falling edge; a discharge current source which is used for determining the slope of the falling edge of the output voltage according to the discharge current of the discharge load capacitor; a switched capacitor digital-to-analog converter which is used for setting the discharge initial voltage of the discharge load capacitor; a buffer which is used for converting a voltage falling edge discharged by the discharge load capacitor into a rising edge and providing a stable output rising edge conversion rate; and a clock and control signalgeneration circuit which is used for receiving the input delay control word dcw and the input clock in and outputting an actual delay control word dcw _ act and a plurality of different clock phases.According to the invention, high linearity in a larger delay time range is realized, and the phase-locked loop has the characteristics of low noise and low power consumption, has high linearity, andis very suitable for being applied to a fractional-frequency phase-locked loop.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a constant slope digital time converter and a control method thereof. Background technique [0002] Under the control of the low-frequency reference clock, the sub-sampling phase-locked loop directly samples the high-frequency output of the oscillator to obtain phase error information, and then adjusts the output frequency of the oscillator through negative feedback control to realize the function of the phase-locked loop. The sub-sampling structure cannot obtain frequency error information, and the loop can theoretically lock at any integer multiple of the reference clock frequency. Since the sub-sampling structure directly samples the oscillator output without using a frequency divider, the power consumption of the system is effectively saved. However, it is also difficult to use the traditional fractional frequency control method based on a ΔΣ modulator (DSM) and a...

AI Technical Summary

Problems solved by technology

Since there is not a completely linear relationship between input control and delay variation, the digital-to-time converter linearity performance of this structure is limited, and it needs to rely on device matching, layout design and detailed simulation data, and the influence on manufacturing process, supply voltage and temperature (PVT) error is very sensitive, often need to calibrate the circuit to meet the design requirements

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