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Teck LEF file verification method and Teck LEF file verification system

A verification method and document technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as inability to expose loopholes, inability to check TechLEF, and inability to solve TechLEF rules.

Active Publication Date: 2020-03-27
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This process is too simple and has low accuracy. The main disadvantages are: 1) It is necessary to repeatedly export the layout data and perform physical verification software inspection, which takes a long time to debug; 2) It cannot solve the over-constraint rules in Tech LEF; 3) It cannot check Tech Each rule of LEF has low accuracy; 4) Since the tested circuit is relatively simple and the integration level is low, it is impossible to expose loopholes

Method used

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  • Teck LEF file verification method and Teck LEF file verification system
  • Teck LEF file verification method and Teck LEF file verification system
  • Teck LEF file verification method and Teck LEF file verification system

Examples

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no. 1 example

[0054] The first embodiment of the Tech LEF file verification method for integrated circuit automatic layout and routing software provided by the present invention includes the following steps:

[0055] S1, forming two test layout graphics according to integrated circuit process design rules, one of the two test layout graphics is a correctly designed test layout graphics, and the other is a wrongly designed test layout graphics;

[0056] S2, using the pending Tech LEF file to respectively verify the two test layout graphics;

[0057] S3, if the correct design of the test layout pattern is verified by the Tech LEF file, and the result of the verification of the incorrectly designed test layout pattern by the Tech LEF file is incorrect, then it is judged that the Tech LEF file is correct, otherwise it is judged that the Tech LEF file is wrong.

[0058] The first embodiment of the Tech LEF file verification method of the present invention can improve the accuracy of the technica...

no. 2 example

[0060] Such as figure 2 As shown, the second embodiment of the Tech LEF file verification method for integrated circuit automatic layout and routing software provided by the present invention includes the following steps:

[0061] S1, forming two test layout graphics according to integrated circuit process design rules, one of the two test layout graphics is a correctly designed test layout graphics, and the other is a wrongly designed test layout graphics;

[0062] refer to image 3 As shown, the correct test layout pattern is the correct layout pattern that satisfies the minimum size of the integrated circuit process design rules, such as 50 nanometers;

[0063] The wrong test layout pattern is an error layout pattern smaller than the correct test layout pattern by a minimum grid point, for example, 49 nanometers; the minimum grid point is defined according to the actual production process under the condition of satisfying the integrated circuit process design rules;

[0...

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Abstract

The invention discloses a Teck LEF file verification method for automatic layout and wiring software of an integrated circuit. The method comprises the following steps: forming two test layout graphsaccording to an integrated circuit technological design rule, one of the two test layout graphs is a test layout graph which is designed correctly, and the other one is a test layout graph which is designed wrongly; respectively verifying the two test layout graphs by adopting a to-be-tested Teck LEF file; and judging that the Teck LEF file is correct if the result of the correct test layout graphverified by the Teck LEF file is correct and the result of the wrong test layout graph verified by the Teck LEF file is wrong, and otherwise, judging that the Teck LEF file is wrong. The invention further discloses a Teck LEF file verification system for the automatic layout and wiring software of the integrated circuit. According to the method, the accuracy of the Teck LEF file can be verified,and the debugging time of the Teck LEF file is shortened.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a Tech LEF file verification method for integrated circuit automatic layout and routing software. The invention also relates to a Tech LEF file verification system for integrated circuit automatic layout and routing software. Background technique [0002] Conventional large-scale process design layout and wiring requires manual layout and wiring, which is low in integration, cumbersome and inefficient. As the process size becomes smaller and the integration level is higher and higher, such as the advanced 14 / 12 / 10 nanometer process, integrated circuit design relies more on automatic layout and routing software as the last step in the digital integrated circuit design process , digital layout design is the most important link, which determines the success of chip design. [0003] Mainstream automatic place and route software (for example, INNOVUS) requires the use of Tech LEF ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/367
Inventor 许烨东杨婷张倩倩
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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