A debugging and verification platform and testing method for RISC-V processor system

A RISC-V, processor system technology, applied in fault hardware testing methods, electrical digital data processing, instruments, etc., can solve the problems of cumbersome SoC verification platform construction and high requirements for boards and cards, so as to improve project parallelism and flexible debugging The effect of high sex and highlighting substantive features

Active Publication Date: 2022-07-19
SUZHOU METABRAIN INTELLIGENT TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Aiming at the problem that the SoC verification platform is cumbersome to build and the requirements for boards are high during the debugging process of the RISC-V system, the present invention provides a debugging verification platform and a testing method for the RISC-V processor system

Method used

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  • A debugging and verification platform and testing method for RISC-V processor system
  • A debugging and verification platform and testing method for RISC-V processor system

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Embodiment 1

[0045] like figure 1 As shown, the technical solution of the present invention provides a debugging and verification platform for a RISC-V processor system. The FPGA-based RISC-V processor system starts the SoC verification platform, including a processor soft core, and the processor soft core passes through a bus. The module communicates with the RAM storage control module and the UART data control module respectively;

[0046] The platform also includes a mode control module, which is respectively connected with the RAM storage control module and the UART data control module;

[0047] The RAM storage control module is connected with a RAM memory; it is used for code instruction storage and program operation;

[0048] The mode control module is connected with a GPIO interface, which is used to generate a control signal to the processor soft core to transform the system mode according to the input signal of the GPIO interface;

[0049]The UART data control module is connecte...

Embodiment 2

[0062] like figure 2 As shown, the technical solution of the present invention provides a test method for a debugging system of a RISC-V processor system. For the debugging platform of the first embodiment, the RISC-V system startup test method of the present invention can be divided into debugging according to GPIO control. and update two modes, including the following steps:

[0063] S1: RISC-V processor starts running;

[0064] S2: The startup code starts running;

[0065] For the RISC-V processor soft core, its operating frequency, BootRom address and RAM bus address need to be correctly configured. The system startup code includes ZSBL, FSBL, BBL and Kernel. In order to save storage resources, try to optimize invalid codes and optimize and simplify Kernel. At the same time, due to the use of the smallest SoC system, redundant hardware initialization code is omitted. The final system startup code file The storage and running space requirements are met (the function and...

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Abstract

The invention provides a debugging verification platform and a testing method for a RISC-V processor system, including a processor soft core, which communicates with a RAM storage control module and a UART data control module respectively through a bus module; the The platform also includes a mode control module, which is respectively connected with the RAM storage control module and the UART data control module; the RAM storage control module is connected with a RAM memory; used for code instruction storage and program running; the mode control module A GPIO interface is connected to generate a control signal to the processor soft core to perform system mode transformation according to the input signal of the GPIO interface; the UART data control module is connected with a UART interface; it is used to control switching according to the transformation of the system mode The mode of the UART interface.

Description

technical field [0001] The invention relates to the technical field of processor design verification, in particular to a debugging verification platform and a test method of a RISC-V processor system. Background technique [0002] FPGA is programmable, flexible, stable, fast and efficient. It is a supplement to ASIC and can also be used as a verification platform for ASIC. [0003] RISC-V is a novel and advanced instruction set that is widely adopted in processor design due to its forward-looking, compact, extensible and open source features. [0004] During the design verification process of the processor, the startup and debugging of the operating system are essential processes. The startup file of the system requires storage space such as SD card or Flash. Building a SoC verification platform for RISC-V processors based on FPGA and adding related peripherals such as SD card or Flash is a relatively time-consuming task, and it also requires an FPGA board. The card needs ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22G06F11/267
CPCG06F11/2247G06F11/2273G06F11/267
Inventor 王贤坤
Owner SUZHOU METABRAIN INTELLIGENT TECH CO LTD
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