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ESD-protected grounded-grid MOS structure

A MOS structure, ESD protection technology, applied in the direction of electrical components, transistors, electric solid-state devices, etc., can solve the problems of increasing the production cost of integrated circuits, redundant layout of integrated circuits, etc., and achieve the effect of simplifying the layout of integrated circuits

Active Publication Date: 2020-04-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present application provides a grounded gate MOS structure for ESD protection, which can solve the problem of complicated integrated circuit layout and increase the production cost of integrated circuits in the related art

Method used

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  • ESD-protected grounded-grid MOS structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] This embodiment provides a grounded gate MOS structure for ESD protection. The grounded gate MOS structure for ESD protection includes: a first conductivity type well region and a second conductivity type well region, and the second conductivity type well region surrounds the first conductivity type well region. Outside the well region of the first conductivity type; a diffusion region of the second conductivity type is formed in the well region of the first conductivity type, and a well ring region of the first conductivity type surrounds the diffusion region of the second conductivity type; a plurality of second conductivity type diffusion regions are formed in the diffusion region of the second conductivity type type injection region, a plurality of second conductivity type injection regions are arranged at intervals, a gate is formed on the interval between two adjacent second conductivity type injection regions, and the gate is grounded; the second conductivity type ...

Embodiment 2

[0034] Based on the first embodiment, in this embodiment, the implanted region of the first conductive type is formed in the well ring region of the first conductive type, and the implanted region of the first conductive type is covered with the first contact structure 410, and one end of the first resistor R1 is connected to the first contact In structure 410, the other end of the first resistor R1 is grounded.

[0035] By grounding the injection region of the first conductivity type in the well ring region of the first conductivity type, the path for electrostatic discharge of the device in the present application is increased, and the problem that the static electricity cannot be released can be avoided.

[0036] refer to figure 2 and image 3 , the first conductivity type is P-type, and the second conductivity type is N-type, that is, a p-type implantation region 120 is formed in the P-type well ring region, the upper surface of the p-type implantation region 120 is cove...

Embodiment 3

[0038]Based on Embodiment 1, in this embodiment, the second conductivity type implantation region can form the source or drain of the device, and the second conductivity type implantation region forming the drain and the second conductivity type implantation region forming the source are alternately arranged cloth. The triode of a MOS transistor is formed between two adjacent implanted regions of the second conductivity type and the well region of the first conductivity type, wherein the well region of the first conductivity type is the gate of the MOS transistor, and the two implanted regions of the second conductivity type One of them is the drain of the MOS transistor, and the other is the source of the MOS transistor; since the implanted regions of the second conductivity type forming the drain and the implanted regions of the second conductivity type forming the source are arranged alternately in sequence, therefore The types of multiple finger-shaped MOS transistors in t...

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Abstract

The invention relates to a semiconductor integrated circuit device, in particular to an electro static discharge(ESD)-protected grounded-grid NMOS tube structure. The grounded-grid MOS structure comprises a first conductive type well region and a second conductive type well region, and the second conductive type well region surrounds the outer side of the first conductive type well region; a second conductive type diffusion region and a first conductive type well ring region surrounding the second conductive type diffusion region are formed in the first conductive type well region; a plurality of second conductive type injection regions are formed in the second conductive type diffusion region, the plurality of second conductive type injection regions are arranged at intervals, a grid isformed on the interval between two adjacent second conductive type injection regions, and the grid is grounded; and a second conductive type injection region is arranged in the second conductive typewell region. The electrostatic protection can be carried out on the input and output ends and the power supply end at the same time through a multi-finger MOS transistor and a double-layer protectionring.

Description

technical field [0001] The present application relates to a semiconductor integrated circuit device, in particular to a gate-grounded NMOS transistor structure for electrostatic discharge (Electro Static Discharge, ESD) protection. Background technique [0002] Electrostatic discharge will pose a fatal threat to integrated circuits. To a large extent, the effectiveness of integrated circuits is caused by electrostatic discharge. Therefore, it is necessary to install ESD protection circuits on the input and output terminals of integrated circuits and power supplies. [0003] In the related art, the most commonly used ESD protection circuit is a gate-grounded MOS, and the gate-grounded MOS is used as an ESD device, and the formed parasitic NPN transistor is usually used to clamp the voltage and discharge the current. Generally, different gate grounding MOSs are required for the input and output terminals and the power supply terminal for ESD protection. In order to improve the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0277
Inventor 邓樟鹏
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP