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Layout design method of novel ESD diode

A layout design and diode technology, which is applied in the layout design field of new ESD diodes, can solve problems such as failure to reach ESD, ESD diode damage, etc., and achieve the effect of improving anti-ESD ability and excellent anti-ESD performance

Pending Publication Date: 2020-04-21
ETOWNIP MICROELECTRONICS BEIJING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, ESD diodes have a fatal shortcoming: when the reverse voltage reaches a certain value, the reverse current suddenly increases, and the ESD diode enters the breakdown region, but if the reverse voltage continues to increase to a certain value, the ESD diode will be destroyed. Complete breakdown and damage, so that it cannot meet the ESD HBM (Human Body Model) 2000V standard

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  • Layout design method of novel ESD diode
  • Layout design method of novel ESD diode
  • Layout design method of novel ESD diode

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0021] Such as Figure 1-4 As shown, the present invention provides a kind of layout design method of novel ESD diode, comprises the following steps:

[0022] First of all, the English abbreviations used in the present invention are: METAL (metal wiring), PW (P well), NW (N well), DNW (deep N well), OD (active diffusion region), N+ (N Type implantation region), P+ (P-type implantation region), STI (shallow trench isolation region), CMOS (complementary metal oxide semiconductor), PSUB (P-type substrate), CONTACT (contact hole).

[0023] The technology that ESD diode of the present invention needs is CMOS technology (with DNW), designs a DNW on the P-type substrate, designs a NW ring and connects with DNW around DNW, forms a large DNW enclosed area now; Then design NW and PW in the DNW closed area, design a PW on both sides of the NW (the NW an...

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Abstract

The invention relates to a layout design method for a novel ESD diode. The method comprises the steps: designing a DNW on a P-type substrate, designing an NW ring at the periphery of the DNW, and enabling the NW ring to be connected with the DNW, thereby forming a large DNW closed region; designing an NW and a PW in the DNW closed region, designing a PW on each of the two sides of the NW, designing a P + injection region on the NW, and designing an N + injection region on the PW; the N + injection region and the P + injection region are isolated by STI, and the N + injection region and the P +injection region are connected to metal through contact holes to form two ends P and N of the ESD diode. According to the invention, the protection of an internal circuit is realized by applying thereverse breakdown of the diode, the middle PW and NW are skillfully not connected to any potential, and the current is guided to the ground through a conduction path in the form of N +--PW--NW-P +, sothat the excellent ESD resistance is realized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a layout design method of a novel ESD diode. Background technique [0002] ESD (electrostatic discharge) will bring devastating consequences to integrated circuits, which is one of the most important reasons for the failure of integrated circuits; The operating frequency is getting higher and higher, which makes the design of ESD protection devices particularly important. Therefore, how to design an ESD device with high reliability and without additional process steps on a limited chip area has become a major consideration for IC designers. [0003] The design purpose of the ESD diode is to prevent the internal normal working circuit from being damaged by the ESD discharge path; when the internal circuit is working normally, the ESD diode is in a cut-off state (high resistance state), and it will not affect the normal operation of the internal circuit; W...

Claims

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Application Information

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IPC IPC(8): G06F30/392H01L27/02
CPCH01L27/0207
Inventor 熊俊朱敏
Owner ETOWNIP MICROELECTRONICS BEIJING CO LTD
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