PLDMOS for ESD protection

Abstract

The invention discloses a PLDMOS for ESD protection. The PLDMOS comprises a P-type epitaxial layer, a channel region and a drift region, wherein the drift region comprises a P well; a first local field oxidation layer is formed on the surface of the P-type epitaxial layer between the P well and the channel region; the first side edge of the first local field oxidation layer is aligned with the P well; a gate dielectric layer and a polysilicon gate are formed on the surface of the channel region; a source region is formed on the surface of the channel region; a drain region is formed on the surface of the P well and is in contact with the first side edge of the first local field oxidation layer in an aligned manner; the drift region also comprises a second P-type region formed on the surface of the P well; the doping concentration of the second P-type region is smaller than that of the drain region; and the second P-type region completely surrounds the drain region and transversely extends to the lower part of a beak structure on the first side edge of the first local field oxidation layer. The PLDMOS can improve the anti-ESD capability of the PLDMOS.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a P-type laterally diffused metal oxide semiconductor (PLDMOS) used for ESD protection. Background technique [0002] In semiconductor integrated circuits, electrostatic discharge (ESD) will cause damage to devices, so ESD protection circuits need to be installed at the input and output ends of integrated circuits for electrostatic protection. Existing devices for ESD protection circuits include laterally diffused metal oxide semiconductors ( LDMOS). Among them, the parasitic PNP device of PLDMOS is mainly conducted by holes, and the mobility of holes is much lower than that of electrons, so its current amplification factor is much smaller than that of NLDMOS, that is, the parasitic NPN device of N-type LDMOS, resulting in the ESD of conventional PLDMOS. The protection capability is extremely low; at the same time, because the working principle of PLDMOS under ESD stress is ...

AI Technical Summary

Problems solved by technology

[0013] figure 1 In the shown existing structure, both the P-well 106 and the drain region 110 are aligned with the first side edge of the first local field oxide layer 104a, and the first side edge of the first local field oxide layer 104a One side edge has a bird's beak structure, so that between the drain region 110 and the P-type epitaxial layer 103, current concentration at the position of the bird's beak structure on the first side edge of the first local field oxide layer 104a is easy to cause ESD The current density is too large, which reduces the ability of PLDMOS to resist ESD

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