Modular multi-chip packaging structure and packaging method thereof

Abstract

The invention discloses a modular multi-chip packaging structure and a packaging method thereof. A plurality of packaging units arrayed on a substrate are packaging units formed by a plurality of chips which are stacked in a stepped manner. The lead ends of the chips stacked in a stepped manner are positioned on the surfaces of the steps, and the lead ends of the plurality of chips are connected through chip wiring. Chip routing is not needed, the packaging volumes of the chips are reduced, and the loss of the electrical property on a wire bond line is avoided. Plastic packaging is carried outon the step surfaces on one sides of the lead ends of the plurality of chips through a first plastic packaging body. An etching circuit connected with the chip wiring is arranged at the bottom of thefirst plastic packaging body, connection wiring is arranged on the substrate, and the etching circuit at the bottom of the first plastic packaging body is connected with the connection wiring on thesubstrate. Finally, the plurality of packaging units are packaged on the substrate through a second plastic packaging body, and the chips are vertically arranged on the substrate after plastic packaging. Different functions can be integrated by packaging the independent modules together, the limitation of traditional multi-chip packaging is well broken through, the structure is simple, and the connection is stable.

Description

【Technical field】 [0001] The invention belongs to the technical field of storage chip packaging, and in particular relates to a modular multi-chip packaging structure and a packaging method thereof. 【Background technique】 [0002] With the development of the semiconductor packaging industry, a multi-chip stacking technology has been used in the packaging of storage products to provide the package with a larger capacity for storing or executing data. The stacking method is superimposed to achieve expansion. The chips of each layer are directly interconnected through wire bond bonding. This method generally requires thinner chip thickness and the bonding wires are suspended, which is easy to cause chip cracks, and longer wire bond bonding is also There will be a loss of electrical performance. Therefore, for this packaging method, higher integration and reliability are crucial. 【Content of invention】 [0003] The object of the present invention is to overcome the disadvant...

AI Technical Summary

Problems solved by technology

[0002] With the development of the semiconductor packaging industry, a multi-chip stacking technology has been used in the packaging of storage products to provide the package with a larger capacity for storing or executing data. The stacking method is superimposed to achieve expansion. The chips of each layer are directly interconnected through wire bond bonding. This method generally requires thinner chip thickness and the bonding wires are suspended, which is easy to cause chip cracks, and longer wire bond bonding is also loss of electrical performance

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