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Data synthesis circuit applied to DDS

A data synthesis and circuit technology, applied in the direction of digital-to-analog converters, etc., can solve problems such as the inability to increase the digital core rate and restrict the development of DDS

Active Publication Date: 2020-04-24
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a data synthesis circuit applied to DDS, to solve the problem that the current digital core rate cannot be improved and restricts the development of DDS

Method used

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  • Data synthesis circuit applied to DDS
  • Data synthesis circuit applied to DDS
  • Data synthesis circuit applied to DDS

Examples

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Embodiment 1

[0022] figure 1 It is a schematic diagram of the DDS circuit used in the data synthesis circuit of the present invention. The circuit is a typical direct digital frequency synthesizer, including a phase accumulator, a phase-amplitude converter, MUX, analog receiving stage, data synthesis circuit and DAC. Config provides device configuration information such as frequency and phase to the phase accumulator. After phase accumulation, phase signals Phase(1)~Phase(m) are generated and passed to the phase-amplitude converter for phase-to-amplitude conversion. The phase-amplitude converter converts the amplitude signals Amp(1)~Amp(m) to MUX. The MUX generates the final parallel sinusoidal digital signals data(1)~data(4) through the analog receiving stage and the data After processing by the synthesis circuit, it is converted into a differential signal and supplied to the DAC to be converted into an analog output Analog_out. Where f clk / m is the m frequency division of the DDS system...

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Abstract

The invention discloses a data synthesis circuit applied to a DDS. The data synthesis circuit comprises a PMOS tube PM1, NMOS tubes NM1 to NM8, an inverter INV and a buffer BUFF. The source end of thePMOS tube PM1 is connected with a power supply VDD, the drain end of the PMOS tube PM1 is connected to the drain ends of the NMOS tubes NM1, NM2, NM3 and NM4 and connected with the inverter INV and the buffer BUFF, and the gate end of the PMOS tube PM1 inputs a DDS clock fclk; the source ends of the NMOS tubes NM1, NM2, NM3 and NM4 are respectively connected with the drain ends of the NMOS tubesNM5, NM6, NM7 and NM8, and the gate ends of the NMOS tubes NM1, NM2, NM3 and NM4 respectively input four paths of interleaved signals Adata (1), Adata (2), Adata (3) and Adata (4) of the DDS; the source ends of the NMOS tubes NM5, NM6, NM7 and NM8 are connected with the ground GND, and the gate ends of the NMOS tubes NM5, NM6, NM7 and NM8 are input to the DDS clock quadruple frequency division fclk / 4.

Description

Technical field [0001] The present invention relates to the field of integrated circuit technology, in particular to data synthesis for DDS. Background technique [0002] DDS (Direct Digital Synthesizer, direct digital frequency synthesizer) is a digital frequency and phase waveform synthesis technology device. It generates a sinusoidal digital signal through an internal digital core and converts it into an analog signal output through an embedded DAC. The device has the advantages of high adjustment accuracy, precise frequency hopping and good stability, and is widely used in the fields of communication, radar and measurement and control. [0003] At present, the digital cores of high-speed DDS are implemented using CODIC or improved CODIC algorithms. The output of the digital cores is mostly single-channel or dual-channel interleaved architecture. The rate of digital cores based on the architecture algorithm is limited by the architecture and process and cannot be too high. It s...

Claims

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Application Information

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IPC IPC(8): H03M1/66
CPCH03M1/66
Inventor 张涛盛炜张皓然
Owner 58TH RES INST OF CETC
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