Multi-block pixel array based on multi-wafer stacking technology

Abstract

The invention discloses a multi-block pixel array based on a multi-wafer stacking technology. The pixel array is formed by periodically arranging a plurality of composite dielectric gate double-devicephotosensitive detectors, wherein the pixel array and a peripheral non-pixel array module are respectively manufactured on an upper wafer and a lower wafer which are different, the pixel array is connected with the non-pixel array module through a through hole between the wafers, and the non-pixel array module comprises a reading module, a high-voltage module, a decoding module and a logic control module; each composite dielectric gate double-device photosensitive detector comprises a photosensitive transistor and a reading transistor, and the photosensitive transistor and the reading transistor both adopt a composite dielectric gate structure; the pixel array is divided into a plurality of working blocks, the composite dielectric gate double-device photosensitive detector of each block is provided with independent word lines and bit lines, the word lines and the bit lines of different blocks are not connected, and the blocks are closely arranged. According to the invention, the transmission speed of a single picture is accelerated, the frame rate of a video is improved, and the authenticity of an ultrahigh-pixel image can be ensured.

Description

Technical field [0001] The invention relates to a composite dielectric gate dual device pixel unit, in particular to a multi-block pixel array architecture based on a multi-wafer stacking technology. Background technique [0002] Image sensors are widely used in today's society, such as mobile phones, digital cameras, various cameras, and defense detection fields. The main imaging detectors currently developed are CCD and CMOS-APS. The basic structure of CCD is a series of MOS capacitors in series. The generation and change of semiconductor surface potential wells are controlled by the voltage pulse sequence on the capacitors to realize the storage of photo-generated charge signals. And transfer readout; each pixel of CMOS-APS is composed of diodes and multiple transistors, and the light signal is obtained by reading the changes before and after exposure. CMOS-APS has received greater attention in recent years due to some advantages. CCD production has extremely high requirement...

AI Technical Summary

Problems solved by technology

In an earlier patent (US6784933B1), the floating gate transistor pixel adopts the NOR structure, and an electrode lead is required between each adjacent pixel, which also reduces the size of the pixel

[0004] However, as the pixel scale continues to expand, no matter whether the array adopts NAND or NOR architecture, the readout time is still the key factor restricting the video frame rate of the imaging chip.

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