Built-in self-test circuit and memory

Abstract

The invention discloses a built-in self-test circuit and a memory. The built-in self-test circuit comprises: a digital voltage-controlled oscillator used for generating a high-frequency clock signal;a clock signal control module which is used for inputting a high-frequency clock signal into the address input channel, the data input channel, the output channel and tested equipment during high-speed testing; an address input channel which is used for inputting a test address signal into the tested equipment according to the clock signal input by the clock signal control module; a data input channel which is used for inputting a test data signal into tested equipment according to the clock signal input by the clock signal control module; and an output channel which is used for receiving andoutputting an output signal of the tested equipment. A digital voltage-controlled oscillator is integrated in the built-in self-test circuit, a high-frequency clock signal is provided for the test, the frequency requirement of a test clock provided by a test machine is reduced, peripheral equipment is simplified, the test time is shortened, and the test cost is reduced.

Description

technical field [0001] The present application relates to the technical field of memory, in particular to a built-in self-test circuit and memory. Background technique [0002] As the feature size of integrated circuits continues to shrink, the integration and complexity of chips continue to increase, and the number of defects that may exist in memory chips, especially in intellectual property (Intellectual Property, IP) cores of memory, also gradually increases. At the same time, memory is also constantly developing in the direction of high capacity, high speed, low power consumption and high integration. These have greatly increased the difficulty of testing memory IP cores. [0003] At present, when testing memory IP cores, external automatic test equipment (ATE) is mainly used to generate test patterns to detect faults in memory IP cores. However, since most memories are high-speed storage, this requires test equipment to be able to The memory provides a higher-frequen...

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Problems solved by technology

[0003] At present, when testing memory IP cores, external automatic test equipment (ATE) is mainly used to generate test patterns to detect faults in memory IP cores. However, since most memories are high-speed storage, this requires test equipment to be able to The memory provides a higher frequency test clock, and the higher the frequency of the output test clock, the higher the cost of ATE, which leads to the problem of higher cost of memory IP core for high-speed testing

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