Multi-power-domain multi-clock-domain first-in first-out queue, integrated circuit chip and computer equipment

Abstract

The invention discloses a multi-power-domain multi-clock-domain first-in first-out queue, an integrated circuit chip and computer equipment. The multi-power-supply-domain multi-clock-domain first-in first-out queue comprises a write logic, a read logic, a write logic power supply domain and a read logic power supply domain, wherein the write logic is located in a write logic power supply domain, the read logic is located in a read logic power supply domain, the write logic power supply domain and the read logic power supply domain are provided with a plurality of level conversion units for completing power supply domain conversion, and the write logic and the read logic are located in different clock domains; each of the integrated circuit chip and the computer equipment comprises the multi-power-domain multi-clock-domain first-in first-out queue. According to the invention, signal transmission delay caused by clock domain conversion of signals of different power domains can be eliminated, and the clock frequency of the system is improved.

Description

technical field [0001] The invention relates to a first-in-first-out (FIFO) queue, in particular to a first-in-first-out queue with multiple power domains and multiple clock domains, an integrated circuit chip and computer equipment. Background technique [0002] At present, there is no first-in-first-out queue solution that directly completes the conversion of multiple power domains in the technical field. When the signals of different power domains are converted to the clock domain, the power domain conversion is often completed through the input interface outside the FIFO, and then enter the FIFO to complete the cross-clock domain conversion function of the signal. Such as figure 1 Shown is the power domain conversion structure diagram of the traditional asynchronous FIFO. Signals related to writing data such as write enable wen, write clock wclk, full signal full, and half full signal half_full are in another power domain, as shown in the box area on the left side of t...

AI Technical Summary

Problems solved by technology

Therefore, before entering the FIFO, because the signal needs to cross different voltage regions, a level conversion unit needs to be added, thereby increasing the delay of signal transmission, and this delay is in the same clock domain, which in turn affects the delay of logic design and reduces System operating frequency

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