Structure and method for semiconductor device

Abstract

Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source / drain regions and a channel region between the source / drain regions; a gate structure over the substrate and adjacent to the channel region; source / drain contacts over the source / drain regions and electrically connecting to the source / drain regions; and a contact protection layer over the source / drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source / drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source / drain regions when gate vias are formedover the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

Description

[0001] This application is a divisional application of the invention patent application entitled "Structure and Method for Semiconductor Devices" with application number 201410507439.3 filed on September 28, 2014. technical field [0002] The present invention relates generally to the field of semiconductor technology, and more particularly, to designing semiconductor devices and methods of forming them. Background technique [0003] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, where each generation has smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (ie, the number of interconnected devices per unit chip area) typically increases while geometry size (ie, the smallest component (or line) that can be made using a fabrication process) decreases. This scaling down process provide...

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Problems solved by technology

This can be problematic especially for FETs with many gate vias because there may not be enough bonding area on the semiconductor device outside the active area

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