A grid topology analysis method based on gpu layered acceleration
An analysis method and power grid topology technology, applied in circuit devices, electrical components, information technology support systems, etc., can solve the problems of reduced parallelism, performance loss, rough reproduction, etc., to achieve high parallelism, time-consuming, The effect of improving parallelism
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment
[0094] The actual grid is tested by using the profile file of the smart grid dispatching system. The test grid model is a network adjustment level grid with a voltage range of 1kV to 500kV, including 11,293 lines, 347 units, 43,040 loads, 6,341 transformers, 10,509 parallel compensators, 3 series compensators, and 94,711 circuit breakers And 168584 knife gates. After topology analysis, there are 10,849 computing nodes, 9,384 computing nodes on the main island, and 118,447 physical nodes.
[0095] The hardware and software configuration of the test platform is as follows:
[0096] serial number name Version 1 Windows operating system Windows 10 Professional (64-bit) 2 CUDA CUDA 10.1 3 CPU Intel i9-9900K 4 GPU NVIDIA TITAN RTX
[0097] The test results are as follows:
[0098]
[0099] The analysis method of the present invention utilizes the characteristics of the grid model to propose a grid topology analysis method based...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


