High-speed DDR single event effect evaluation system and method based on FPGA

Abstract

The invention relates to a high-speed DDR4 single event effect evaluation system and method based on an FPGA. The high-speed DDR4 single event effect evaluation system comprises a DDR4 to be tested, ahigh-energy irradiation experiment terminal or pulse laser irradiation platform and a single event test system. A DDR4 active region to be tested is located in the center of the high-energy irradiation experiment terminal or the pulse laser irradiation platform, and the DDR4 to be tested is in real-time communication with the single-particle test system; the lower computer system of the single particle test system is used for performing read-write operation on the DDR4 to be tested according to an instruction sent by the upper computer system and sending read-back data of the DDR4 to be tested to the upper computer system; and the upper computer system is used for issuing an instruction, carrying out read-write operation on the to-be-tested DRR4 in real time, carrying out read-back verification on written data, and discriminating single-particle soft errors, thereby realizing testing of the single-particle effect of the to-be-tested DRR4. The method can be widely applied to the fieldof single event effect testing.

Description

technical field [0001] The invention relates to an FPGA (field programmable gate array)-based high-speed DDR4 (fourth generation double data rate synchronous dynamic random access memory) single event effect evaluation system and method, belonging to the field of particle testing. Background technique [0002] Single event effects are an important factor affecting the use of advanced electronic components in orbit. Due to the reduction of device process size, the increase of device integration, the reduction of operating voltage, and the increase of operating frequency, the impact of single event effects on electronic components is more serious. At the same time, while the high speed increases the sensitivity of the device to the single event effect, it also brings great difficulties to the evaluation and testing of the single event effect. Therefore, the research on the single event effect of advanced high-speed devices has become a research hotspot and difficulty in the f...

AI Technical Summary

Problems solved by technology

However, with the increase in the complexity of the structure and function of the memory to be tested, and the increase in the operating frequency of the memory, it is difficult for the existing control logic to be compatible with advanced memories such as DDR4.

For such devices with higher testing requirements, the logic in the main control FPGA is not limited to the configuration and control of several modules, and the state machine is used to operate in steps and categories, the process is cumbersome and the application object is single

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