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Memory device

A technology of memory elements and voltage drivers, applied in the field of page buffers, which can solve the problems of narrow on/off operation margin of serial selection lines

Active Publication Date: 2020-07-31
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when moving to more advanced CMOS technologies, the on / off operating margin of the string select line will only get narrower

Method used

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Embodiment Construction

[0091] In the drawings, the same element numbers generally represent the same parts in different drawings. Moreover, the drawings are not necessarily to scale, emphasis instead generally being placed upon the technical principles described in the specification. In the following implementation manners, the embodiments for implementing the technical means disclosed in this specification will be described in detail in conjunction with the attached drawings.

[0092] refer to Figure 1 to Figure 7 A detailed description is provided for embodiments of the invention. The embodiments are presented only to illustrate the technical features of the present invention, and are not intended to limit the scope of the claims of the present invention. The scope of protection of the present invention should be defined by the appended claims. Those skilled in the art will be able to make equal modifications and changes according to the descriptions in the following specification without depa...

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Abstract

A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program / inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupledto corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the firstswitch transistor above the first supply voltage level to turn on the first switch transistor.

Description

technical field [0001] The disclosure of this specification relates to a memory device, and in particular to a page buffer of a non-volatile memory for improving switching margins on select gates and other switching transistors. Background technique [0002] NAND flash memory is widely used as a storage medium for mobile devices, solid-state disks in notebook computers and servers, and other data processing systems. As the data density on NAND flash memory chips increases, page operations using a large number of global bit lines to access memory cells in parallel for pages of data have become quite common. [0003] With the advancement of complementary metal oxide semiconductor (CMOS) technology, CMOS devices require smaller device areas, operate at higher speeds and lower power consumption, and use lower operating Voltage. The channel length and channel width become smaller, the thickness of the gate oxide (GOX) shrinks, and the operating clock frequency (clock frequency)...

Claims

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Application Information

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IPC IPC(8): G11C16/30G11C5/14
CPCG11C5/147G11C16/30G11C5/145G11C7/12G11C16/0483G11C16/12G11C16/24G11C11/5621G11C11/5671H03K19/20
Inventor 叶腾豪刘逸青
Owner MACRONIX INT CO LTD