GGNMOS ESD protection device structure based on SOI process

Abstract

The invention discloses a GGNMOS ESD protection device structure based on an SOI technology. The structure comprises an SAB layer, P-type doped source-drain units SP, N-type doped source-drain units SN, a polycrystalline gate POLY, a device active region TO and contact holes W1. P-type doped source and drain units of a strip-type NMOS tube are segmented; the body contact of the device is designedbetween every two sections of P-type doped source-drain units. A P-type doped source and a P-type doped drain of a strip-type NMOS tube are segmented; the body contact of the device is designed between every two P-type doped source drains, the N-type doped source drain units of the strip-type NMOS tube are ingeniously segmented through the structure, the range of an SN injection layer and the range of an SP injection layer are defined by the segments respectively, the process is achieved through photoetching, and by means of the design, on one hand, the area is saved, and on the other hand, the body contact is more sufficient; TLP test evaluation shows that under the same area, the ESD resistance of the SOI GGNMOS device is obviously improved by 1.2 times or above compared with that of a traditional SOI GGNMOS device.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a GGNMOS ESD protection device structure based on SOI technology. Background technique [0002] ESD protection technology has been the focus of research in the field of microelectronics. According to statistics, failures caused by ESD account for more than 37% of integrated circuit failures, and this proportion is further increasing with the reduction of device feature size. [0003] The characteristics of high speed, low leakage, good sub-threshold characteristics, latch-up immunity and low soft error rate provided by SOI technology have made it one of the most competitive technologies widely used. Since the bottom of the SOI device is isolated by a thick buried oxide layer, and the surroundings of the device are also fully dielectrically isolated by SiO2, SOI devices and circuits are very sensitive to ESD stress on the one hand; on the other hand, com...

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Problems solved by technology

[0004] The object of the present invention is to provide a kind of GGNMOS ESD protection device structure based on SOI process, to solve the failure caused by ESD in the above-mentioned background technology and account for more than 37% in the failure of integrated circuits, and this ratio increases with the device The shrinking feature size is further raising the issue

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