3D memory device and manufacturing method thereof

Abstract

The application discloses a 3D storage device and a manufacturing method thereof. The manufacturing method of the 3D storage device includes: forming a step-shaped insulating stack structure on the semiconductor substrate, each step including a sacrificial layer and an interlayer insulating layer located below the sacrificial layer; forming a protective layer on at least part of the exposed surface of the sacrificial layer layer; form a dielectric layer covering the insulating stack structure above the protection layer; replace the sacrificial layer with a gate conductor layer to form a gate stack structure; form a conductive conductor connected to the gate conductor layer on at least one of the steps The channel, wherein the protective layer serves as a stop layer for forming a conductive channel at least partially in contact with the gate conductor layer. The manufacturing method forms a protective layer by treating the surface of the stacked structure, and uses the protective layer as a stop layer to perform an etching process to form a step area contact, which reduces the etching difficulty and improves the reliability of the memory device.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and manufacturing methods thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, three-dimensionally structured memory devices (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] In the 3D NAND structure, it mainly includes a gate stack structure, a channel column penetrating the gate stack structure, and a conductive channel. The gate stack structure is used t...

AI Technical Summary

Problems solved by technology

As the number of stacked layers in the 3D NAND structure continues to increase, the total film thickness of the dielectric layer continues to increase, which will lead to an increase in the difficulty of etching deep holes / deep grooves

Generally, the difficulty of etching deep holes / grooves is reduced by appropriately reducing the thickness of the single-layer dielectric stack, but the etching stop layer corresponding to the contact hole used to form the conductive channel in the step area will also be correspondingly thinned and increased. Reduce the difficulty of etching and reduce the process window

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