Multi-board synchronous acquisition circuit and method based on JESD204B

Abstract

The invention discloses a multi-board synchronous acquisition circuit and method based on JESD204B. The output frequency alignment of a PLL module of a single signal acquisition board can be realizedthrough a PLL synchronous signal; and a ZERO DELAY (zero delay) mode is utilized to realize alignment of the output clock phase of the PLL and the input clock phase of the phase discriminator, so phase alignment between the output frequencies of the PLL modules in the signal acquisition boards is realized, and finally, synchronous data acquisition of the ADC modules in the signal acquisition boards is realized.

Description

technical field [0001] The invention relates to the technical field of signal processing, in particular to a multi-board synchronous acquisition circuit and method based on JESD204B. Background technique [0002] The sampling rate of ADC / DAC is getting higher and higher, and the data throughput is getting bigger and bigger. Especially for ADC / DAC above 500MSPS, it is difficult to meet the design requirements with traditional CMOS and LVDS. JESD204B came into being. [0003] As the third-generation standard of JEDEC (Solid State Technology Association), JESD204B has a link rate of 12.5Gb / s, and has a data interface that requires less board space, lower setup and hold timing requirements, and converters and logic devices. advantage of smaller packages. [0004] Although compared with the existing interface formats and protocols, the JESD204B interface has many advantages such as fast speed and less occupied IO pins, but in the multi-board multi-chip ADC synchronous acquisitio...

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Problems solved by technology

[0004] Although compared with the existing interface formats and protocols, the JESD204B interface has many advantages such as fast speed and less occupied IO pins, but in the multi-board multi-chip ADC synchronous acquisition circuit based on JESD204B, how to realize the channel of multi-board multi-chip ADC It is still difficult to have deterministic delay. In the problem of synchronous data acquisition by ADC between multiple boards, more complex circuit design and special clock circuit are required.

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