MOS transistor output editing transmission type multi-system and decimal bit weight adder
A MOS tube, output editing technology, applied in the computer field, can solve problems such as slow development and achieve the effect of effective hardware support
Pending Publication Date: 2020-09-01
胡五生
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[0003] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware to support multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of computer is almost zero, in view of this situation, the present invention proposes a kind of simple and effective multi-value calculation implementation circuit, especially the effective method of ten-value calculation and realizes multi-value, especially ten-value addition and subtraction with binary hardware , multiplication, division arithmetic operations and the key circuits of logic operations, which are called "quantization logic" and their circuits
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[0118] refer to figure 2 (1), 2(2), 2(3), use the circuit described in claim 3 in the two patent applications 201711119713.x "multi-ary arithmetic operator for quantization logic" as the unit Circuit, and use the gate of each MOS tube as a set of bit weight input, the drain of each MOS tube as another set of bit weight input, the gate and drain of the MOS tube are output according to the addition rule and the standard position of the fractal diode request, according to figure 1 The addition table of (1) is edited and connected, thus forming the same addition module with the output standard, the standard output is equal to the 0 module, and the original output is equal to the 1 module. This is output equal to 0 module press figure 2 The method described in (1) and figure 1 (1) The addition table, edit the output bit weight information and connect to the corresponding output bit weight bus. This is an output equal to 1 module in accordance with figure 2 The method descri...
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The invention discloses an MOS transistor output editing transmission type multi-system and decimal bit weight adder composed of MOS transistors. The MOS transistor output editing transmission type multi-system and decimal bit weight adder is composed of multi-valued addition modules in different forms. The multi-valued addition module is provided with an output standard equal to 0 module, an equal to 1 module, an equal to 2 module... an equal to N module; the module is formed by combining and connecting arithmetic units which are connected in different modes, and the arithmetic units are formed by permutation and combination of the circuits according to the claim 3 of the patent application 201711119713.x. The selection of each unit according to the carry system and the two input addend are added, the units with the same unit bits of 'sum ' values are arranged together to form operation modules with different scales, grid electrodes of all the units in the modules form input of a group of bit weight data, drain electrodes of all the units in the modules form input of a group of bit weight data, and fractal output carry 1 outputs in the units are connected together to serve as module carry output.
Description
technical field [0001] The invention relates to the field of computer technology, in particular to a "MOS tube output editing transmission type multi-ary and decimal bit weight adder" which is one of the basic hardware for realizing a multi-valued computer [0002] technical background [0003] So far all computers and their related digital systems are binary. Although multi-valued computing has many advantages, it develops very slowly because there is no key hardware supporting multi-valued computing. It can be said that multi-valued computers, especially decimal The realization of computer is almost zero, in view of this situation, the present invention proposes a kind of simple and effective multi-value calculation implementation circuit, especially the effective method of ten-value calculation and realizes multi-value, especially ten-value addition and subtraction with binary hardware , Multiplication, division arithmetic operations and key circuits of logic operations ar...
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IPC IPC(8): G06F7/38
CPCG06F7/38
Inventor 胡五生
Owner 胡五生