Chip packaging structure and method

Abstract

The invention relates to the technical field of semiconductors, and particularly relates to a chip packaging structure and method. The structure comprises a substrate, a rewiring layer, a first chip unit and a first packaging layer, wherein the substrate is provided with an accommodating space; the rewiring layer is arranged in the accommodating space and on the surface of the substrate; the firstchip unit is arranged on the rewiring layer in the accommodating space and is provided with a first conductive connection point; the first conductive connection point is connected with the rewiring layer; and the first packaging layer fills the accommodating space. According to the chip packaging structure provided by the invention, the rewiring layer is arranged in the accommodating space of thesubstrate and on the surface of the substrate, and the first chip units are arranged in the accommodating space and connected with the rewiring layer, so that the space size of the packaging structure is saved, the integration degree is improved, the accommodating space is filled with the first packaging layer, the first chip unit is packaged, and the problem of large warping is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and method. Background technique [0002] When packaging the first chip unit and the second chip unit chip, the current more traditional solutions include: placing the first chip unit and the second chip unit on one side of the packaging substrate, or placing the first chip unit and the second chip unit on both sides of the packaging substrate respectively. A chip unit and a second chip unit. [0003] In these two solutions, the first chip unit and the second chip unit are completely plastic-sealed with a plastic sealing layer, and when packaged, a large amount of plastic sealing material needs to be used in the packaging process, which is not conducive to the heat dissipation of the package structure, and is also prone to relatively high heat dissipation. Large warping problem leads to low product yield; and both the first chip unit and the sec...

AI Technical Summary

Problems solved by technology

[0005] In view of this, the embodiment of the present invention provides a chip packaging structure and method to solve the problems of large volume, low integration and large warpage in the existing chip packaging structure

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