Gate voltage bootstrap sampling circuit

Abstract

The embodiment of the invention provides a gate voltage bootstrap sampling circuit. The gate voltage bootstrap sampling circuit comprises a sampling circuit, a bootstrap circuit, an output switch circuit and a digital switch circuit, wherein the sampling circuit comprises an NMOS tube M5 and a PMOS tube M14. A source electrode of the NMOS tube M5 is connected with a source electrode of the PMOS tube M14, a drain electrode of the NMOS tube M5 is connected with a drain electrode of the PMOS tube M14, a source electrode of the NMOS tube M5 is connected with a signal source, and a first clock signal is input into a grid electrode of the PMOS tube M14; the bootstrap circuit is used for acquiring a signal source according to the digital switching circuit and the output switching circuit and outputting bootstrap voltage to the sampling circuit according to the signal source; the output switch circuit is used for controlling charging of the bootstrap capacitor and on-off between the anode of the bootstrap capacitor and the sampling circuit; and the digital switch circuit is used for controlling the connection and disconnection between the negative electrode of the bootstrap capacitor and the sampling circuit. The embodiment of the invention provides a gate voltage bootstrap sampling circuit. The linearity is improved.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a gate voltage bootstrap sampling circuit. Background technique [0002] Analog-to-digital converters bridge the digital and analog realms and are integral to the interaction of computers and all end devices with the natural world. The sampling circuit is the first module that the analog signal goes through before it enters the SAR ADC (successive approximation register Analog-to-Digital Converter, successive approximation analog-to-digital converter), and its accuracy has a direct impact on the overall accuracy of the SAR ADC. [0003] In the related art, the sampling circuit may be a gate voltage bootstrap sampling circuit. figure 1 A gate voltage bootstrap sampling circuit is shown, and its working process is as follows: [0004] (1) CLKSB in the figure is the inverse signal of CLKS. When CLKS is at low level and CLKSB is at high level, NMOS tubes M9 an...

AI Technical Summary

Problems solved by technology

[0006] However, in actual implementation, due to the parasitic capacitance Cp in the circuit, the calculation formula of the gate voltage of the sampling tube M8 is: It can be seen that the bootstrap capacitor Cb must be large enough to ensure that the bootstrap voltage reaches VDD+Vin when it is input to the gate of the sampling tube M8, which makes the linearity of the sampling tube M8 limited by the bootstrap capacitor Cb, which is not conducive to Improving the Accuracy of Sampling Circuit

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