Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof
A technology for contact pads and semiconductors, which is applied to semiconductor devices, semiconductor/solid-state device components, and electrical solid-state devices, etc., can solve the problems of inconsistent electrical structure on the contact plug, abnormal electrical structure on the contact plug, etc. Avoid electrical structural anomalies, improve dense/sparse effects, improve consistency
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[0037] The memory and its forming method proposed by the present invention will be further described in detail below in conjunction with the drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use inaccurate scales, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0038] Please refer to figure 1, an embodiment of the present invention provides a contact pad layout of a semiconductor device, and the contact pad layout includes a main layout area 10 and a first edge layout area 11. Wherein, the main layout area 10 is provided with a plurality of main contact pad patterns 101, the shape and size of each of the main contact pad patterns 101 are similar, and all the main contact pad patterns 101 are arranged in a checkerboard pattern, adjacent to...
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