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Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof

A technology for contact pads and semiconductors, which is applied to semiconductor devices, semiconductor/solid-state device components, and electrical solid-state devices, etc., can solve the problems of inconsistent electrical structure on the contact plug, abnormal electrical structure on the contact plug, etc. Avoid electrical structural anomalies, improve dense/sparse effects, improve consistency

Pending Publication Date: 2020-09-08
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0004] The object of the present invention is to provide a semiconductor device and its contact pad layout, contact pad structure and mask combination to solve the problem of optical proximity effect and dense / sparse effect of circuit patterns in existing semiconductor devices such as dynamic random access memories. This leads to the inconsistency of the electrical structure connected to the contact plug inside the core area and the abnormal electrical structure of the contact plug connected to the border of the core area.

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  • Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof
  • Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof
  • Semiconductor device and contact pad layout, contact pad structure and mask plate combination thereof

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Embodiment Construction

[0037] The memory and its forming method proposed by the present invention will be further described in detail below in conjunction with the drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use inaccurate scales, which are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0038] Please refer to figure 1, an embodiment of the present invention provides a contact pad layout of a semiconductor device, and the contact pad layout includes a main layout area 10 and a first edge layout area 11. Wherein, the main layout area 10 is provided with a plurality of main contact pad patterns 101, the shape and size of each of the main contact pad patterns 101 are similar, and all the main contact pad patterns 101 are arranged in a checkerboard pattern, adjacent to...

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Abstract

The invention provides a semiconductor device and a contact pad layout, a contact pad structure and a mask plate combination thereof. A first edge layout area is arranged on one side of a main layoutarea where a main contact pad pattern is located; the area of each first edge contact pad pattern in the first edge layout area is greater than that of each main contact pad pattern; a main contact pad of a core region and a dummy contact pad of an interface region at the boundary of the core region or between the core region and a peripheral region are formed on the basis of the contact pad layout, so that the top surface area of the virtual contact pad can be greater than that of the main contact pad, further, when the main contact pad and the virtual contact pad are connected with an electrical structure, the size of the electrical structure connected to the virtual contact pad can be increased so as to improve the dense / sparse effect of the circuit pattern between the core region and the peripheral region, the consistency of the electrical structure connected to the main contact pad can be improved, and meanwhile the problem that the electrical structure connected to the main contact pad at the boundary of the core region is abnormal can be avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and its contact pad layout, contact pad structure and mask combination. Background technique [0002] Various techniques have been used to integrate more circuit patterns in a limited area of ​​a semiconductor substrate or wafer. Due to the difference in circuit pattern spacing, integrated circuits are generally divided into device-dense areas (Dense), device-sparse areas (ISO) and device-isolated areas. It is an area where the device density is low (that is, the devices are relatively sparse), and the device isolated area is an area where relatively sparse areas and dense areas are set separately. As the critical dimensions of semiconductor devices continue to decrease, the density of circuit patterns and / or device heights continue to increase, subject to the resolution limit of the optical exposure tool and the density difference between device-de...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544
CPCH01L23/544H01L2223/54493H01L2223/54426
Inventor 童宇诚曾依蕾詹益旺
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD