Semiconductor layered device with data bus inversion

Abstract

Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input dataresponsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.

Description

Background technique [0001] High data reliability, high-speed memory access, low power consumption, and reduced chip size are required features of semiconductor memories. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking chips (eg, dies) vertically and interconnecting the chips using through-substrate vias (TSVs). Benefits of 3D memory devices include shorter interconnects (which reduce circuit delay and power consumption), a large number of vertical vias between layers (which allow wide bandwidth buses between functional blocks in different layers), and relatively small footprints. Thus, 3D memory devices enable higher memory access speeds, lower power consumption, and reduced chip size. Example 3D memory devices include hybrid memory cubes (HMC), high bandwidth memory (HBM), and wide I / O dynamic random access memory (DRAM). [0002] For example, high-bandwidth memory (HBM) is a type of memory that in...

AI Technical Summary

Problems solved by technology

The DBI calculation should be performed within 1 cycle of the read clock signal READ; however, it takes a relatively long time to complete the DBI calculation because the DBI calculator 12 is composed of a large number of logic gates

Therefore, the cycle of the read clock signal READ is required to be long enough to complete the DBI calculation, and thus the data transfer speed is inhibited by the DBI operation

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