Self-adaptive digital clock taming system

Abstract

The invention discloses a self-adaptive digital clock taming system, which is characterized in that an input signal frequency multiplication unit is used for carrying out digital frequency multiplication on an external input signal, so that the system precision is improved; digital phase discrimination is carried out through a digital phase discriminator, a phase discrimination result is sent to an error statistics unit to calculate frequency and phase errors, and statistics and temporary storage are carried out; and then flexible large-dynamic-range traceable frequency division processing isachieved through a multi-stage flexible anti-lock-loss frequency division control circuit, digital frequency division is performed in combination with any fractional frequency division unit, and feed-back is performed to a digital phase discriminator to perform closed-loop regulation control so as to achieve synchronization with a target signal frequency.

Description

technical field [0001] The invention belongs to the technical field of clock taming, and more specifically relates to an adaptive digital clock taming system. Background technique [0002] Many electronic systems such as automatic control, AD sampling, and DA synthesis require high-precision clocks. At present, high-precision clocks generally require the use of atomic clocks, which are not only expensive to obtain, but also large in size and complex in system. [0003] In order to reduce the cost and volume of high-precision clocks, satellite timing technology and tame clock technology have been gradually developed. Through satellite timing technology, high-precision 1PPS signals can be obtained, and the signal error can be less than 10 -11 ~10 -12 , and then through taming technology, to achieve local output high-precision 10MH Z or 5MH Z High-precision clock, the general accuracy can reach 10 -10 ~10 -11 . [0004] The taming method of the digital clock has only tw...

AI Technical Summary

Problems solved by technology

[0004] The digital clock taming method only has two states of locking and unlocking, which not only requires high precision of the tamed clock, but also slow taming speed and easy to lose lock. If the output clock is required (usually 5MH Z ) with an accuracy of 10 -10 ~10 -11 , the monitoring time threshold is up to 2×10 3 ~2×10 4 S, taming time at least 10 5 ~10 6 S, the tamed clock needs to use a constant temperature crystal oscillator (accuracy 10 -8 ~10 -9 ), once unlocked takes a long time to tame to relock

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