Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve the problems of reducing the performance of LDMOS devices, affecting the application prospects of LDMOS devices, and large on-resistance, so as to reduce on-resistance, Effects of reduced pitch and low on-resistance

Active Publication Date: 2022-05-10
JOULWATT TECH INC LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the basis of this structure, the on-resistance between the source terminal and the drain terminal of the LDMOS device will be very large, which will reduce the performance of the LDMOS device and affect the application prospect of the LDMOS device.

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Embodiment Construction

[0033] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0034] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly above another layer or another region, or between it and Other layers or regions are also included between another layer and another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

[0035]If it is to describe the situation directly on another layer or ...

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The device comprises: a substrate, an epitaxial layer, a source region, a drain region, a gate structure and sidewalls. The source region includes: a P-type well region; at least A first implant region; at least one second implant region; a first shallow doped region; a second shallow doped region; formed in the entire source region and covering all the first implant region, the second implant region, the first shallow doped region region and the third implanted region of the second shallowly doped region, wherein the third implanted region is an N-type implanted region, and the doping concentration of the third implanted region is greater than that of the first and second shallowly doped regions, and less than the doping concentration of the first and second implanted regions. The present invention effectively reduces the on-resistance between the source end and the drain end by adding an N-type implantation region with a concentration higher than that of the shallowly doped region in the source end region.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the wide application of Lateral Double Diffused MOS Transicor (LDMOS) in integrated circuits, the performance requirements for LDMOS are also getting higher and higher, such as generally requiring devices to have a higher turn-off breakdown voltage (off -BV) and lower on-resistance (Rdson). [0003] Generally speaking, the way to reduce the on-resistance of LDMOS devices is to continuously increase the concentration of the drift region and at the same time, through various RESURF (Reduced SURface Field, reduce the surface battery) theories, so that it can be completely depleted, so as to obtain low conductivity. On-resistance, and maintain a high off-breakdown voltage. However, the device size can also be reduced to make the device area smaller, thereby reducing the on-resistanc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/08H01L21/336
CPCH01L29/7816H01L29/086H01L29/66681
Inventor 韩广涛
Owner JOULWATT TECH INC LTD
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